Pulse or digital communications – Cable systems and components
Reexamination Certificate
1999-12-22
2003-04-01
Tse, Young T. (Department: 2634)
Pulse or digital communications
Cable systems and components
C375S360000, C713S400000
Reexamination Certificate
active
06542552
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an improved data transmitter for transmitting digital data from a driver to a receiver.
In recent years, a “DS-Link” technique has been adopted to transmit data from a driver to a receiver as in the IEEE 1394 standards. According to the DS-Link technique, data is transmitted using two types of signals: data signal and strobe signal. Specifically, if the data changes its value every time like 0, 1, 0, 1, . . . , then the strobe signal remains the same. Alternatively, if the same data value of 0 or 1 appears consecutively, then the strobe signal changes its level. An exclusive-OR is obtained based on the level transitions of these two types of signals, thereby reproducing desired data.
According to the DS-Link technique, either the data or strobe signal changes its level during one transmission period (or one cycle) of data. Thus, compared to a method of transmitting data that has been latched in synchronism with every edge of a clock signal, a much greater margin should be ensured in view of skewing between a clock signal and the data to be transmitted.
However, as the data transmission rate has reached the order of several gigabits, one cycle time of data is now less than 1 ns. If data is transmitted at such a high speed, then the DS-Link technique is no longer applicable to reproduction of desired data because of the following reasons. Specifically, the shorter one cycle time of data is, the larger percentage of the cycle time the output timing lag or propagation time lag between the data and strobe signals accounts for at the driver or on the transmission line. In such a situation, an edge of the data signal output comes too close to an associated edge of the strobe signal output. As a result, the receiver can obtain no exclusive-OR for these two types of signals anymore.
Nevertheless, if only data is output from the driver without adopting the DS-Link technique (i.e., with no strobe signal output), then the receiver should latch the data in synchronism with an internal clock signal. In such a situation, a skewing problem of a different type happens between the data and internal clock signals this time.
SUMMARY OF THE INVENTION
An object of the present invention is transmitting accurate data from a driver to a receiver at high speeds by outputting only the data from the driver without outputting any strobe signal and by getting the data latched by the receiver in synchronism with an internal clock signal. For that purpose, the skew between the data and internal clock signals is eliminated or at least greatly reduced according to the present invention.
Another object of the present invention is getting accurate data latched by the receiver even if the internal clock signal has delayed with respect to the data.
To achieve this object, if data in transition should be latched (i.e., if erroneous data is possibly latched), then the data is latched in a different way from the ordinary one (i.e., in synchronism with the internal clock signal). The “level transition” of data generally means that the data value changes from one value (before the transition) into the other (after the transition). Thus, when such data in transition should be latched, data with a value opposite to the previous one is latched according to the present invention.
A data transmitter according to the present invention includes: a driver for outputting digital data onto a transmission line; and a receiver for latching the data, which has been output on the transmission line, in synchronism with an edge of an internal clock signal. The receiver includes: a transition pulse generator for generating transition pulses, each representing a transition of the data that has been output on the transmission line; and a data latching circuit for latching data with a value opposite to that of another data that has been output on the transmission line during a previous cycle if any edge of the internal clock signal at the receiver overlaps with associated one of the transition pulses.
In one embodiment of the present invention, the receiver may include means for controlling the phase of the internal clock signal. The phase control means adjusts the period of the internal clock signal by comparing an edge of the data that has been output onto the transmission line to an associated edge of the internal clock signal.
In this particular embodiment, the phase control means preferably operates while each said transition pulse is being applied from the transition pulse generator.
In an alternate embodiment, the driver may include a clock signal transmitter for transmitting a periodic clock signal defining the period of the data that will be output onto the transmission line. The receiver may include an internal clock generator for generating the internal clock signal of the receiver responsive to the periodic clock signal received from the clock signal transmitter.
In another embodiment of the present invention, the data transmitter may further include additional transmission lines. The driver may include a marker for placing a reference mark at an appropriate location of each of a series of data items that will be output onto the transmission lines. The receiver may include: a plurality of FIFO memories for storing the series of data items that have been output on the transmission lines; and a sorter for receiving the reference marks from the marker and sorting out the series of data items that have been received at the FIFO memories based on the reference marks.
In the data transmitter according to the present invention, the transition pulse generator generates the transition pulse in each transition period of the data, during which erroneous data might be latched on an associated edge of the clock signal. If the internal clock signal rises at an edge overlapping with the period during which the transition pulse is being applied, then the data is not latched in synchronism with the clock signal. Instead, the data latching circuit latches data with a value opposite to that of the previous cycle one. As a result, accurate data can be received. On the other hand, in the non-transition periods of the data, i.e., while no transition pulses are being applied, the data is latched normally in synchronism with the internal clock signal, thus latching accurate data, too.
In addition, according to the present invention, the phase control means can adjust and match the period of the internal clock signal to that of the data. Accordingly, even if a train of the same data value (zeros or ones) appears consecutively (i.e., even while no transition pulses are being applied), the boundary between those data is identifiable accurately. As a result, even such data can be latched correctly and normally responsive to the internal clock signal.
Moreover, according to the present invention, the driver not only outputs the data at regular intervals, but also transmits the periodic clock signal defining the period of the data to the receiver. In response to the periodic clock signal, the receiver generates the internal clock signal. As a result, the period of the data can be accurately matched up to that of the internal clock signal at the receiver. If clock generators are provided for both the driver and receiver alike, then the clock frequencies of these generators should be precisely matched up to each other. In contrast, according to the present invention, such a requirement is no longer imposed. In addition, since there is no need for the receiver to control the phase of the internal clock signal, the configuration of the receiver can be simplified.
Furthermore, where a plurality of transmission lines are provided (i.e., a parallel link is established), the data items are stored in respective FIFO memories by way of the transmission lines. Then, the data items stored on these FIFO memories are sorted out by the sorter based on the reference marks provided from the driver. That is to say, the data items that have been stored on the respective FIFO memories sequentially are sorted out to
Terada Yutaka
Yoshikawa Takefumi
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Tse Young T.
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