Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-04-27
2003-09-02
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S747000, C257S773000, C257S778000, C257S780000, C257S787000, C257S788000, C257S789000, C257S790000
Reexamination Certificate
active
06614111
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P2000-134327 filed Apr. 28, 2000, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having bumps, a method for fabricating the same, and a method for forming bumps.
More specifically, the present invention relates to a semiconductor device having bumps able to ease thermal stress to prevent damage due to thermal stress and therefore of high reliability, a method for fabricating the same, and a method for forming bumps.
Along with the increasingly small size of electronic apparatuses, attempts have been made to use compact semiconductor packages of sizes similar to the size of a chip of a flip-chip structure. A large number of electronic circuits are integrated on such a small package, so many connection terminals are necessary. On the other hand, due to the reduced size, the problem arises that the space for arranging these connection terminals is insufficient. In such a small semiconductor package, DIPs or other connection terminals of the related art cannot be used.
As a solution to this problem, attempts have been made for flip chip mounting where a large number of small projecting electrodes (bumps) are formed on the bottom surface of a semiconductor integrated circuit chip, many electrodes are formed on a printed wiring board at positions corresponding to those bumps, and the electrodes on the wiring board and the bumps formed on the semiconductor integrated circuit chip are directly bonded. Such flip chip mounting has the advantage that many bumps can be formed even on the bottom surface of a semiconductor integrated circuit chip of a limited space.
As a method for connecting bumps and electrodes, attempts have been made to seal a semiconductor integrated circuit chip and a wiring board by a resin to connect and affix them.
Summarizing the problem to be solved by the invention, a large number of semiconductor integrated circuit chips are of a type using silicon for their semiconductor substrates. The linear thermal expansion coefficient of a silicon chip is much smaller than that of a wiring board. For example, the former is no more than 10% of the latter. As a result of the large difference of the linear thermal expansion coefficients, thermal stress appears when the temperature changes.
In most cases, the linear thermal expansion coefficient of the semiconductor integrated circuit chip is also largely different from that of the sealing resin. Similarly, the linear thermal expansion coefficient of the wiring board is often different from that of the sealing resin.
As a result of the difference of the linear thermal expansion coefficients, when the temperature rises during operation of the semiconductor integrated circuit chip, thermal stress appears between the semiconductor integrated circuit chip and the wiring board between which the sealing resin is interposed.
In a flip-chip structure designed for compactness, there is no mechanism for easing stress such as a lead frame. Therefore, if flip chip mounting is adopted, there could be deformation of the semiconductor integrated circuit chip, decline of bonding between bumps and electrodes, or even loss of the bonded state.
As shown here, although a reduced size is aimed at with flip chip mounting, sometimes the reliability of the semiconductor device could decline because of poor bonding or loss of bonding caused by thermal stress.
Accordingly, it is desirable to improve the reliability against thermal stress for a flip chip mounting semiconductor device which does not have a mechanism such as a lead frame for easing stresses.
SUMMARY OF THE INVENTION
An object of the present invention is to find the conditions for increasing the reliability against thermal stress in a flip chip mounting structure.
Another object of the present invention is to provide a flip chip mounting semiconductor device of high reliability and a method for fabricating such a semiconductor device on the basis of the above conditions.
Still another object of the present invention is to provide a method for forming bumps on a semiconductor integrated circuit chip on the basis of the above conditions.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a wiring board formed with a plurality of electrodes, a semiconductor integrated circuit chip formed with a plurality of bumps, and a sealing resin for bonding the electrodes and bumps at corresponding positions and further surrounding the bonding portions of the electrodes and bumps to adhere the wiring board and semiconductor integrated circuit chip, wherein each individual bump is formed under the condition that quantities &PHgr;A, H, and F are in the region defined by the following formula A:
a
L
<((&PHgr;
A×F
)/
H
)<
a
U
(A)
where,
&PHgr;A denotes the top diameter of a bump bonded with an electrode,
H denotes the height of a bump, defined as the distance from the semiconductor integrated circuit chip to the end of the bump bonded with an electrode,
F denotes the linear thermal expansion coefficient of the sealing resin,
a
L
denotes the lower limit, and
a
U
denotes the upper limit.
Up until now, it was thought that high bumps were preferable. This is because the large number of bumps formed on a semiconductor integrated circuit chip are uneven in height, the large number of electrodes formed on the wiring board are uneven in height, the bottom surface of the semiconductor integrated circuit chip is not completely flat, and the surface of the wiring board is not completely flat. Furthermore, when a bump and a electrode are bonded, the semiconductor integrated circuit chip and the wiring board may warp or deform. They may also deform due to shrinkage of the sealing resin at time of curing. High bumps are preferable when considering the margin for eliminating such unevenness.
Studies and experiments of the inventors of the present invention have revealed that there are optimal values to dimensions of individual bumps defined by the above formula A.
Note that when considering the height of bumps, the height of electrodes formed on the wiring board should be considered, too.
This is because due to the height of the bumps and the height of the electrodes, a gap is maintained between the wiring board and the semiconductor integrated circuit chip to prevent contact of the wiring board and the semiconductor integrated circuit chip, and the conditions of the sealing resin are optimized for interposition between the wiring board and the semiconductor integrated circuit chip for maintaining bonding of bumps and electrodes and for sealing.
Preferably, the sealing resin is a thermosetting resin.
Further, as a condition for the above formula to stand, the linear thermal expansion coefficient of the wiring board is 10 times that of a semiconductor integrated circuit chip and the linear thermal expansion coefficient of the thermosetting sealing resin is in the range from 20 to 70 ppm.
Specifically, the bump comprises gold, and the electrode comprises a conductive metal.
It is desirable that the electrode be harder than the bump. When applying pressure for bonding, it is desirable that the electrode not deform while the bump deforms.
Preferably, the lower limit a
L
is about 100, and the upper limit a
U
is about 125.
Specifically, the bump height H is in the range from about 20 &mgr;m to about 25 &mgr;m.
More specifically, the top diameter &PHgr;A of a bump is no more than 50 &mgr;m.
These regions of the bump height and top diameter &PHgr;A are realistic bump dimensions giving good reliability against thermal stress.
According to a second aspect of the present invention, there is provided a semiconductor device comprising a wiring board formed with a plurality of electrodes, a semiconductor integrated circuit chip formed with a plurality of bumps, and a sealing resin for bonding the electrodes and bumps at corresponding positio
Honda Noriyuki
Iwatsu Satoshi
Elms Richard
Holland & Knight LLC
Menz Douglas
Sony Corporation
Steadman Lewis T.
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