Clock control method and circuit

Details Clock control method and circuit Clock control method and circuit

2001-01-08

2003-07-29

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S294000

Reexamination Certificate

active

06600354

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a method of controlling clock signals and to a clock control circuit. More particularly, the invention relates to a clock signal control method and circuit ideal for application to a semiconductor integrated circuit device synchronized to a system clock to control internal circuitry. More specifically, the invention relates to a circuit that uses a timing averaging circuit for clock control, as well as to a clock control circuit that uses a timing averaging circuit in a synchronizing circuit such as a delay-locked loop, phase synchronizing loop or synchronous delay circuit.
DESCRIPTION OF THE RELATED ART
In a semiconductor integrated circuit synchronized to a system clock to control internal circuitry, the entirety of the internal circuitry is controlled by executing a given circuit operation every cycle of the clock.
In order to assure operation that takes variance due to system clock jitter into account in a semiconductor integrated circuit of this kind, the length of time in clock cycle that can actually be used for circuit operation is obtained by subtracting jitter time from the period of the clock. Accordingly, if we let Tmin represent the minimum time necessary for circuit operation executed in one clock cycle, then it will be necessary for the minimum period tCKmin of the clock to be set to a time Tmin+Tjitter, namely a length of time obtained by adding jitter time Tjitter to Tmin, as shown in FIG.
16
.
Further, in order to reduce delay time between the system clock and an internal clock or to multiply the frequency of the clock in a semiconductor integrated circuit synchronized to a system clock to control the internal circuitry, the conventional practice is to use a phase-locked loop (PLL), a delay-locked loop (DLL) or a synchronous delay circuit. However, these clock control circuits can be a source of clock jitter and are susceptible to jitter of the system clock, in which case locking time is prolonged. Thus, these circuits tend to degrade the synchronization characteristic.
A PLL is effective in reducing jitter depending upon how the PLL is set up. In a PLL, a clock having a frequency and phase the same as those of an external clock is generated by a voltage-controlled oscillator (VCO)
105
configured for feedback, as shown in FIG.
21
. In this arrangement, the jitter component of the system clock is suppressed by a phase comparator
102
, a charge pump
103
connected to the output of the phase comparator
102
and a loop filter
104
connected to the output of the charge pump
103
, thus making it possible to reduce jitter of the clock generated by the VCO
105
. The charge pump
103
receives the output (UP and DOWN signals, etc.) from the phase comparator
102
and the output node thereof is charged or discharged, whereby a voltage corresponding to the phase difference between the clock and the output of the VCO
105
is applied as the input voltage of the loop filter
104
.
Because a PLL is a feedback circuit, however, a long period of time on the order of several hundred to several thousand cycles is required until the clock stabilizes. In addition, if jitter is too large, there is the possibility that the PLL will not remain locked.
In a DLL, on the other hand, a clock having a phase the same as those of an external clock is generated by a voltage-controlled delay circuit
115
configured for feedback, as shown in
FIG. 22. A
problem that arises, therefore, is that external clock jitter passes through the delay circuit as is and is transmitted to the internal circuitry from a clock driver
106
.
In a synchronous delay circuit, as shown in
FIG. 23
, a pair of delay circuit chains
901
,
902
and a dummy delay circuit
905
, which comprises an input buffer dummy
905
A and a clock driver dummy
905
B, are used to subtract the delay time (td
1
+td
2
) of the dummy delay circuit
905
from the clock period tCK of a clock whose phase is the same as that of an external clock, whereby a delay quantity tV is obtained. The delay quantity tV is measured as the length of time of travel through the delay circuit chain
901
, and the delay is reproduced by the other delay circuit chain
902
, thereby synchronizing the internal clock to the external clock.
The synchronous delay circuit, which eliminates clock skew in a short synchronization time, finds use in high-speed clock synchronizing circuits thanks to the simplicity of the circuitry and the low power consumption. Reference is had to the following literature which cites examples of synchronous delay circuits of this kind:
[1] The specification of Japanese Patent Application Laid-Open (KOKAI) No. 8-237091;
[2] Jin-Man Han et al., “Skew Minimization Technique for 256M-bit Synchronous DRAM and beyond.” 1996 Symp. on VLSI Circ. pp. 192-193;
[3] Richard B. Watson et al., Clock Buffer Chip with Absolute Delay Regulation Over Process and Environment Variations.” Proc. of IEEE 1992 CICC (Custom Integrated Circuits Conference), 25.2; and
[4] Yoshihiro OKAJIMA et al, “Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface.”IEICE TRANS. ELECTRON., VOL. E79-C, NO. 6 JUNE 1996 pp. 798-807.
As shown in
FIG. 23
, the synchronous delay circuit has a basic structure which includes a set of delay circuits, namely the delay circuit
901
, which is used to measure a fixed time difference, and the dummy delay circuit
905
providing a delay time corresponding to the delay time td
1
+td
2
, which is obtained by adding the delay times td
1
and td
2
of an input buffer
903
and clock driver
904
, respectively.
In order for the dummy delay circuit
905
to make the delay time equal to the sum of the delay times td
1
and td
2
of the input buffer
903
and clock driver
904
, respectively, there are many cases where the dummy delay circuit
905
is constructed using the input buffer dummy
905
A, which comprises circuitry exactly identical with that of the input buffer, and the clock driver dummy
905
B.
The delay circuit
901
and delay circuit
902
each consist of delay circuits having equal delay times.
The purpose of the delay circuit
901
is to measure a fixed period of time, and the purpose of the delay circuit
902
is to reproduce this period of time. These objects can be achieved by passing the signal through the delay circuit
901
for the measured period of time and arranging it so that the signal can be passed through the delay circuit
902
using a number of delay elements equivalent to the number of delay elements traversed by the signal in the delay circuit
901
.
The following approach may be adopted to enable a signal to be passed through the delay circuit
902
using a number of delay elements equivalent to the number of delay elements traversed by the signal in the delay circuit
901
: The delay circuit
901
and delay circuit
902
are divided into two types depending upon their signal propagation directions and, in order to decide the length of the delay circuit
902
, the delay circuits are divided into two types depending upon whether the terminus is selected or the entire path of the circuit is selected, giving four types of delay circuits.
Specifically, if the delay circuit
901
and delay circuit
902
are divided into two types depending upon their signal propagation directions, the delay circuits
901
,
902
can have the same direction, with the length of the delay circuit
902
being decided on the side of its output terminals in order to decide the number of elements in the delay circuit
902
, as illustrated in
FIGS. 26 and 27
, or the delay circuits
901
,
902
can have opposite signal propagation directions, with the length of the delay circuit
902
being decided on the side of its input terminals in order to decide the number of elements in the delay circuit
902
, as depicted in
FIGS. 24 and 25
.
Further, in order to decide the length of the delay circuit
902
, there are two types of arrangements, namely one in which the terminus is selected and one in wh

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