Circuitry, architecture and method(s) for synchronizing data

Details Circuitry, architecture and method(s) for synchronizing data Circuitry, architecture and method(s) for synchronizing data

1999-09-08

2003-07-15

Vo, Don N. (Department: 2631)

Pulse or digital communications

Synchronizers

Reexamination Certificate

active

06594325

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The present application may relate to co-pending application Ser. Nos. 09/391,865 and 09/391,967, each filed Sep. 8, 1999.
FIELD OF THE INVENTION
The present invention relates to data communication devices generally and, more particularly, to circuitry, architecture and method(s) for synchronizing data.
BACKGROUND OF THE INVENTION
Conventional data communication devices use a word synchronization event to synchronize the data received. The synchronization event precedes the receipt of the data. The event is the transmission of 16 consecutive special characters, such as K28.5 characters. An elasticity buffer (EB) is reset and data from each channel is synchronized. The skew allowed between the channels must meet a predetermined tolerance, such as +/−2 bit times.
When synchronizing multiple channels across chips, a master channel must be arbitrarily selected whose Word Sync Output (WSO) signal is connected to all other Word Sync Inputs (WSI). The WSO is a three bit serial protocol informing the other chips to add or delete idle characters. Because of the limitation of the EB, the maximum skew allowed among channels is still +/−2 bit times. However, the skew allowed among the channels within the chip is larger than +/−2 bit time.
SUMMARY OF THE INVENTION
One aspect of the present invention concerns an apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.
Another aspect of the present invention concerns a circuit comprising a storage circuit configured to read and write data one or more addresses in response to one or more first decoded control signals and a decoder circuit configured to present an output data signal in response to (i) the one or more addresses, (ii) a fixed address and (iii) one or more second decoded control signals.
The objects, features and advantages of the present invention include providing a communications device that may (i) use a common crystal, (ii) align parallel frequencies to reduce or eliminate skew between channels, (iii) operate in a system where a number of PLLs are locked, and/or (iv) operate to deskew parallel frequencies in a configuration where data is stripped and parallel decoding is normally lost.


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Gabriel Li, “Circuitry, Architecture and Method(s) for Synchronizing Data”, U.S. Ser. No. 09/391,967, Filed Sep. 8, 1999.

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