Registers – Records – Conductive
Reexamination Certificate
2000-09-15
2003-06-10
Lee, Michael G. (Department: 2876)
Registers
Records
Conductive
C235S380000, C235S382000, C235S487000
Reexamination Certificate
active
06575373
ABSTRACT:
CROSS REFERENCE TO THE RELATED APPLICATION
The subject application is related to subject matter disclosed in the Japanese Patent Application No.Hei11-264537 filed in Sep. 17, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a signal processing device provided with a processor (CPU), a memory and so forth. In particular, the present invention is related to a signal processing device installed within a security equipment, an encryption device such as an IC card (smart card), an electronic lock and so forth.
2. Description of the Related Art
In the prior art technique, a security equipment such as an encryption device installed within an IC card (smart card), an electronic lock and so forth is provided generally with a signal processing device having a CPU, a memory and so forth for the verification of a password.
The instruction execution cycle times as required for executing the respective instructions by means of the signal processing device are different from each other depending upon the execution types thereof. Accordingly, a respective instruction is executed at a predetermined time point after the signal processing device initiates instruction processing so that it is possible to analyze the operation of the signal processing device relating to the timing of the execution of a particular instruction, for example, by monitoring the time elapsed just after initiating a certain stage of the instruction processing triggered by resetting the internal CPU or receiving an external signal.
Because of this, for example, it becomes possible to determine a particular instruction a predetermined time period after initiating a certain stage of instruction processing by monitoring an internal phenomenon which can be externally observed. Hence, there is a fear that the operation of the signal processing device is analyzed by an unauthorized person.
Accordingly, pseudo routines, which are useless and harmless, are inserted into the program routine executed by the signal processing device, as means for introducing irregularity to the sequence of instructions as executed in order to deceive the analysis of the operation of the signal processing device.
More specifically speaking, for example, the program routine including the pseudo routine may be executed in order to run the pseudo routine between the main routine for verifying a password and the internal phenomenon which is externally observable. Particularly, the pseudo routine is repeated between the main routine and the internal phenomenon for a variable number of times, i.e., the frequency of repetition is determined at random for each appearance of the program routine.
However, in the prior art technique making use of such a pseudo routine, there is a problem that the processing time in the signal processing device tends to becomes longer. More specifically speaking, while a random variation of the order of one to several clocks in the processing time is sufficient to obfuscate the internal phenomenon under external analysis, several tens of clocks are required to run the pseudo routine from the main routine. Furthermore, there is substantial overhead on the processing time of the signal processing device when the pseudo routine is repeated for a plurality of times.
The present invention has been made in order to solve the shortcomings as described above. It is an object of the present invention therefore to provide a signal processing device with an improved reliability and an enhanced impenetrability against encryption analysis while avoiding substantial overhead on the processing time of the signal processing device.
SUMMARY OF THE INVENTION
In order to accomplish the above and other objects, when a signal input to a signal processing device is processed by a processor, a wait signal is transmitted from a random signal generation circuit to the processor in a non-periodic manner in order to halt the processor at random. The operation state of the processor is maintained when halted, and the halted operation is continued from the operation state as maintained when resumed.
In accordance with the present invention, since the operation of the processor can be halted in a non-periodic manner, it is possible to prevent the operation of the processor from being analyzed by observing the internal phenomena of the processor. Particularly, in the case of the present invention, substantial overhead on the processing time of the signal processing device can be avoided by providing a short halting time period
Meanwhile, also in accordance with an modification of the present invention, the clock signal as inputted to the processor can be deferred in a non-periodic manner. In the case of the modification, it is possible to make more implicated patterns of the operation of the processor by the combination of deferring the clock signal in a non-periodic manner and the wait signal as output from the random signal generation circuit also in a non-periodic manner. As a result, the analysis of the operation of the signal processing device becomes furthermore difficult.
Also, in accordance with another modification of the present invention, the processor receives a password as said signal and matches the password against secret data stored in a memory in order to verify whether or not the password is in agreement with the secret data.
In the case of the modification, it becomes possible to make difficult the analysis of the operation by externally observing the internal operation while the processor performs signal processing for matching the password and the secret data. The reliability of the signal processing device can therefore be improved.
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patent: 5406624 (1995-04-01), Tulpan
patent: 5852290 (1998-12-01), Chaney
patent: 5936543 (1999-08-01), Matsumoto
patent: 6010074 (2000-01-01), Kelly et al.
patent: 6098888 (2000-08-01), Praden
patent: 6196459 (2001-03-01), Goman et al.
patent: 6296191 (2001-10-01), Hamann et al.
patent: 6402028 (2002-06-01), Graham et al.
patent: 8-249239 (1996-09-01), None
Lee Michael G.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Paik Steven S.
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