Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-06-19
2003-07-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S531000
Reexamination Certificate
active
06600181
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for reducing the source current noise in a semiconductor integrated circuit and further relates to a decoupling circuit formed on a semiconductor chip as well as a technique effectively utilized for a method of determining an inductance of an inductor constituting the decoupling circuit.
2. Description of the Related Art
In a system using the semiconductor integrated circuit (hereinafter referred to as an LSI), a high frequency component of a change of current in the LSI generates an electromagnetic wave as well known in the art. The following techniques for suppression of electromagnetic radiation have been known. More particularly, the specification of JP-A-6-309050 discloses a semiconductor substrate
12
of the semiconductor device
10
having a constant current source element
24
interposed in a source voltage supply line
26
supplying a source voltage to the internal circuit
22
and a capacity means
30
connected to a ground voltage supply line
28
supplying a ground voltage to the internal circuit
22
and the source voltage supply line
26
. Also, the specification of JP-A-8-288462 discloses a semiconductor integrated circuit device having a circuit grout
5
, which includes a CPU
5
, a bus
8
, which is provided so as to surround the circuit group
5
, and a terminal pad
9
which is arranged outside the bus
8
, wherein the semiconductor integrated circuit device is also provided with constant potential lines
1
a
and
3
a
, which have a part routed to increase the parasitic inductance and reach the circuit group
5
from the constant potential terminal pads
2
and
4
. Further, the specification of JP-A-2-25037 discloses that an inductance component
5
and a resistance component
5
R are added to an LSI
1
for increasing voltage drop inside the LSI
1
, wherein, since the voltage drop inside the LSI increases, the voltage drop outside the LSI is relatively decreased, reducing the noise level outside the LSI.
The technique for providing a decoupling circuit comprised of an inductor and a bypass capacitor on a printed circuit board faces a problem that the number of parts packaged in the printed circuit board increases to reduce the packaging density and increase costs of fabrication.
Further, the technique in which a constant current element is provided for a source voltage supply line on a semiconductor chip and a capacity means is connected between a source voltage line and a ground line has a disadvantage that the substantial source voltage level in the internal circuit is decreased by the constant current element on the source voltage supply line.
Furthermore, in the technique in which a fixed potential line, that is, source voltage line and a ground potential line are pulled about on a chip to increase a parasitic inductance component so as to suppress a change in source voltage, the ability of response to signals is degraded to make this technique undesirable. Also, in the technique of increasing inductance and resistance components by pulling about the source wiring in the LSI, the internal load or the source impedance increases, having a disadvantage that the change of source voltage in the internal circuit increases.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor integrated circuit that can decrease the adverse influence upon the operation of the internal circuit and effectively prevent a high frequency component of source current change from generating an electromagnetic wave.
Another object of the invention is to provide a design technique that can easily determine an inductance of a source inductor and a source capacitance necessary for suppressing the source current noise to a desired value or less through simulation in designing the semiconductor integrated circuit.
The above and other objects and novel features of the present invention will become apparent from a description of the present specification taken in conjunction with the accompanying drawings.
Representative ones of inventions disclosed in the present application will be outlined as below.
Namely, according to one aspect of the present invention, in an LSI having a plurality of power supply pads and a plurality of ground potential pads, wiring conductors having impedances which are substantially equal to each other are provided between the plurality of power supply pads and a power supply line in the LSI.
More specifically, there are provided a plurality of first power supply pads, a plurality of second power supply pads, a first power supply line for supplying a first power supply voltage applied to the plurality of first power supply pads to an internal circuit, a second power supply line for supplying a second power supply voltage applied to the plurality of second power supply pads to the internal circuit, and a plurality of inductors each connected between each of the plurality of first power supply pads and the first power supply line and each being comprised of a wiring conductor in the form of a horse shoe, a U-shape, a frame shape, a spiral or a loop that makes a loop around the internal circuit by ¾ turns or more so as to make the plurality of inductors may have mutually substantially equal impedances reaching nodes at which the internal circuit connects to the first power supply line.
With the above construction, the wiring conductors or inductors are respectively provided between the plurality of external power supply terminals and the power supply line in the semiconductor integrated circuit, whereby a change in source current passing through the inductors can be suppressed to ensure that propagation of the source current noise to the outside of the semiconductor integrated circuit can be prevented effectively to prevent the generation of an electromagnetic wave due to a high frequency component of the source current noise. Further, since any wiring conductors or inductors are not pulled about between the plurality of external ground terminals and the ground line in the LSI, the ability of response to signals is not degraded. In addition, the plurality of inductors respectively connected to the plurality of external power supply terminals can increase the source inductance in total. Further, the plurality of inductors connected in parallel can decrease the source impedance relative to the internal circuit.
Preferably, the wiring conductors constituting the plurality of inductors may each be formed so as to make a loop around the semiconductor chip and so as to be connected between the corresponding power supply pad and the first power supply line so that the direction of current flowing through each wiring conductor may be the same. This is because the parallel arrangement of a plurality of lines in which currents flow in opposite directions decreases the inductance. An inductor of a desired inductance can be formed without increasing the chip size to a substantially large extent in comparison with the conventional semiconductor integrated circuit devoid of inductor.
More preferably, each inductor may include a first wiring layer formed to make a loop around the semiconductor chip and a second wiring layer formed to overlap the first wiring layer, the start end of the first wiring layer may be connected to any one of the plurality of first power supply pads and the termination end of the first wiring layer may be connected to the start end of the second wiring layer, and the termination end of the second wiring layer is connected to the first power supply line. In other words, the inductor takes the form of a double coil comprised of mutually overlapping upper and lower two wiring layers. Through this, the inductance can be increased without increasing the occupation area of the internal circuit.
Preferably, each inductor may include a first wiring layer formed to make a loop around the semiconductor chip and a second wiring layer formed to overlap the first wiring layer, and the first wiring layer may be connected to the second
Kamohara Shiro
Otake Shigenori
Yokomizo Goichi
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Nelms David
Nhu David
LandOfFree
Semiconductor integrated circuit and designing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and designing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and designing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3096002