Television – Receiver circuitry
Reexamination Certificate
2001-01-12
2003-09-02
Hsia, Sherrie (Department: 2614)
Television
Receiver circuitry
C348S726000, C348S735000
Reexamination Certificate
active
06614490
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital television (TV) receiver using a vestigial sideband (VSB) system, and timing recovering apparatus and method for the digital TV receiver.
2. Description of the Related Art
A high definition television (HDTV) is a next-generation digital TV system developed so that a viewer in a living room can feel the impression in a theater as it is. In comparison to a present analog TV, the HDTV has a much better resolution and a wider aspect ratio, and provides a multichannel sound at a level of a compact disc.
In the United States, Europe, and Japan, the standardization of such a digital TV has been expedited by preparing a broadcasting type and standard in their own ways. In the United States, the transmission format adopts the vestigial sideband (VSB) system proposed by Zenith. In a compression format, MPEG is adopted for video compression, and Dolby AC-3 is adopted for audio compression. Also, the display format is prescribed to be compatible with the existing display method.
For digital transmission of video data compressed by the above-described standard, an error correction coding (ECC) is performed on the compressed video data. At this time, in order to facilitate the data recovery at a receiving part, a synchronizing (sync) signal prepared in a prearranged period is inserted between the error-correction-coded data.
The sync signal is briefly classified into two, a data segment sync signal and a field sync signal.
Here, as shown in
FIG. 1
, one segment is composed of a data segment signal of 4 symbols and data of 828 symbols. One frame is composed of 313 data segments, which are one field sync segment including a training sequence signal, and 312 general data segments.
At a transmission part such as a broadcasting station, a transmitted signal passes through a mapper for changing the power of the signal to a desired power level before it is transmitted. For example, in case of an 8VSB signal for ground broadcasting, the output level of the mapper one among 8-stage symbol values (i.e., amplitude levels) of −168, −120, −72, −24, 24, 72, 120, and 168. Also, according to the prearrangement, the mapper compulsorily prepares and inserts a 4-symbol data segment sync signal among every 828 symbols, and a field sync signal among every 313 data segments. At this time, the prearranged form of the data segment sync signal is 1, −1, −1, and 1 in logic, and the allocated mapper output levels are ‘120’ when the sync signal is ‘1’, and ‘−120’ when the sync signal is ‘0’. In other words, the data segment sync signal has two levels that continuously alternate for each data segment.
FIG. 2
a
shows an output form of the segment sync signal in the 8VSB transmission system for ground broadcasting, and
FIG. 2
b
shows the low-pass-filtered waveform of the sync signal. The signal actually received in the receiving part is the low-pass-filtered signal.
In the receiving part such as a TV receiver as shown in
FIG. 3
, when a VSB-modulated radio frequency (RF) signal is received through an antenna, a tuner
101
selects a frequency of a desired channel by tuning, and converts the selected frequency into a intermediate frequency (IF) signal. A frequency phase locked loop (FPLL) section
102
modulates the IF signal outputted from the tuner
101
to I and Q channel signals of a baseband, and locks their frequencies and phases.
The FPLL section
102
is a circuit where a frequency tracking loop and a PLL are integrated, and serves to lock the frequency first, and then locks the phase if the frequency is locked.
An analog-to-digital (A/D) conversion section
103
converts the I channel signal of the FPLL section
102
into 10-bit digital data, and outputs the digital data to a sync signal detection section
104
. Here, the Q channel signal is used only for carrier recovery.
The sync signal detection section
104
detects the data segment sync signal, field sync signal, etc., inserted in the transmitted signal using the 10-bit digital data from the A/D converter
103
, and outputs the detected signals to an equalization and error correction section
106
. The equalization and error correction section
106
performs an equalization with respect to the data segment sync signal, field sync signal, etc., recovered by the sync signal detection section
104
to correct a linear distortion of amplitude that causes an interference among symbols, and a ghost caused by the signal reflected from a building, mountain, etc., using a training signal, corrects errors produced through a transmission channel, and outputs the equalized and error-corrected signal to a video decoder
107
. The video decoder
107
decodes the equalized and error-corrected signal by an MPEG algorithm to form a video signal that a viewer can view.
At this time, an advanced television systems committee (ATSC) VSB transmission system of the United States digital TV (DTV) type carries only data on the transmitted signal.
Accordingly, the receiving part as shown in
FIG. 3
should use the same clock signal as used for transmission to recover the data. This function is performed by a timing recovery section
105
.
According to the currently proposed ATSC standard, the timing recovery is to be performed using the data segment sync signal regularly inserted by the transmission part.
FIG. 4
is a block diagram of a general timing recovery section
105
. Referring to
FIG. 4
, an analog-to-digital conversion (ADC) section
103
converts the input analog I-channel signal into a digital signal, and outputs the digital signal to a segment sync detection section
104
-
1
of the sync signal detection section
104
and to a timing error detection section
201
of the timing recovery section
105
. The segment sync detection section
104
-
1
detects a position of the segment sync signal from the digital I-channel signal, and produces a timing enable (timen) signal, PWM enable (pwmen) signal, etc., from the detected segment sync signal. At this time, the timen signal is used as an enable signal of the timing error detection section
201
that extracts timing information, and the pwmen signal is used as an enable signal of a pulse width modulation (PWM) section
202
that converts an output of the timing error detection section
201
so that a converted signal can be used in a charging pump
203
.
Here, the timing error detection section
201
can be implemented by a quadrature filter. Specifically, the timing recovery section
105
performs the timing recovery only in a segment sync section after detecting the segment sync signal, and the quadrature filter for extracting the timing information operates in the segment sync section.
The output of the timing error detection section
201
is converted into an up/down signal of the following charging pump
203
by the PWM section
202
. The output of the charging pump
203
is inputted to a VCXO
205
, after passing through a loop filter
204
, to control the VCXO
205
. The VCXO
205
adjusts an A/D clock outputted to the ADC
103
.
As described above, the timing recovery section
105
recovers the timing to be used as the A/D clock of the A/D conversion section
103
using the data segment sync signal detected by the sync detection section
104
.
However, the above-described timing recovery method using the circuit of
FIG. 4
shows a very weak characteristic if a strong two-symbol-delayed ghost is added to the original signal and inputted. Specifically,
FIG. 5
a
shows a pattern of the data segment sync signal in case that a one-symbol-delayed ghost exists. In this case, the segment sync pattern is maintained.
FIG. 5
b
show a pattern of the data segment sync signal in case that a two-symbol-delayed ghost exists. In this case, the segment sync pattern is distorted due to the two-symbol-delayed ghost applied thereto, and thus, a correlation value between the distorted pattern and the original segment sync pattern inserted in the transmission part cannot be obtained.
In this cas
Gu Young Mo
Hong Sung Ryong
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