Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-01-18
2003-06-03
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185200, C365S185240
Reexamination Certificate
active
06574139
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to reading dual bit memory cells, and more specifically to a method for reading dual bit memory cells using multiple reference cells with two side read and a y-decoder device configured for the two side read.
BACKGROUND OF THE INVENTION
Conventional non-volatile memory such as flash memory has memory cells that each store multiple bits of data. One type of memory cell is a dual bit memory cell that can store two bits of data in a single cell.
FIG. 1
is a structural illustration of a prior art dual bit memory cell. Memory cell
10
includes a gate
12
, a storage nitride layer
14
having a left storage region
20
and a right storage region
22
each capable of storing one bit of data as a level of electron charge, e.g.
24
, two n-type diffusions n
1
and n
2
, in a substrate layer
16
, that serve as a source or a drain depending upon whether the cell is being programmed, read or erased, and a channel region
18
in the substrate layer
16
between n
1
and n
2
, wherein current may flow to indicate the state of the cell. The memory cell may also, instead of having a left and right nitride storage region, be configured with floating gates for charge storage.
To program charge
24
, for example, in the right storage region
22
, a high voltage, e.g. 8.5 to 10.5V, is placed on gate
12
, between 4-6 volts is placed on n
2
, which while programming functions as the drain, and n
1
, which functions as the source, is grounded at 0V. The combination of these voltages on memory cell
10
causes channel hot electron injection that injects electrons into region
22
that localize near n
2
. To read charge
24
stored in memory cell
10
, the roles of source and drain are reversed, between 3.5-4.5 V are placed on gate
12
, between 1-1.6 V is placed on the drain n
1
, and the source n
2
is grounded at 0V. If charge is stored, the threshold voltage (“Vt”) of memory cell
10
will be close to the voltage of gate
12
. This creates a small voltage differential that is insufficient to turn on memory cell
10
, and little current flows through channel
18
, thereby indicating a low programmed state or a programmed data bit “0”. However, if no charge is stored, as is the case with respect to storage region
20
, the Vt of the cell is much lower than the voltage on gate
12
. This creates a large enough voltage differential to turn on memory cell
10
. This allows a significantly larger current to flow through channel
18
, indicating a high programmed state or an erased data bit “1”.
A Y-decoder is used to read dual-bit memory cells in virtual ground architectures. Three selections are required in the y-decoding. The y-decoder needs to select a drain, a source, and a bit line next drain to pre-charge and hold voltage during read to avoid current from draining to the next bit line.
FIGS. 2A-2B
illustrate a prior art y-decoder
30
for reading a dual-bit memory cell. Y-decoder
30
has byte select (BSx) and column select (CS) decoders. There are global metal bit lines (MBL) after the column select decoders, and local diffusion bit lines (DL) for each sector after sector select decoder (SELn). In order to have multiple selections, 4 sector select (out of 8), and 4 column select are selected. Moreover, to read one side of the memory cell, one BSD is selected for drain, one BSG is selected for grounding source, and one BSP is selected for pre-charging and holding the bit line voltage next to drain. Thus, six y-decoding selections are required, i.e., the circled and triangled transistors for BDS, BSG, and BSP in FIG.
2
.
Since two bits of data may be stored in memory cell
10
, it has four possible data states “11”, “10”, “01” and “00”, and each state can be differentiated by setting the Vt of memory cell
10
to a certain value, i.e. by storing a certain level of charge in each storage region. In an array of such cells, the range of Vt to distinguish each state can be clearly identified at the beginning of the life of the memory cells when they are initially programmed, such that accurate data may be obtained when reading the cells. However, over time through the end of cell life, changes in the cell and other phenomena create inaccurate readings.
FIG. 3
illustrates an example of the Vt distributions for data stored in an array of memory cells. Graph
32
shows the Vt distributions for all four data states at the beginning of the cells' life, and graph
34
shows the Vt distributions for all four data states at the end of the cells' life. The graphs indicate a shift, a decrease, in the Vt distribution for all four data states. The Vt decreases due to loss of stored charge during cell life, which in turn lowers complimentary bit disturb. This complementary bit disturb phenomenon occurs when one side of a memory cell is programmed, wherein the Vt of the other side is increased. The harder one side is programmed, the more the Vt of the other side is increased.
The charge loss and resulting decrease in complementary bit disturb and shift in the Vt distributions presents a problem when reading data from the memory cells. As
FIG. 3
illustrates, it is difficult to program a large enough Vt window between the data states to distinguish between a data “0” and a data “1” at the end of cell life. Therefore, at certain Vt it is difficult to distinguish between data states 01 and 10.
What is needed is a method for reading a dual bit memory cell that increases the chance of obtaining an accurate data reading throughout memory cell life, particularly at the end of the cell's life. What is also needed is a y-decoder architecture utilizing this more accurate reading method.
SUMMARY OF THE INVENTION
The present invention is directed at addressing the above-mentioned shortcomings, disadvantages, and problems. The present invention provides for a method for reading at least one programmed dual bit memory cell using a plurality of programmed dual bit reference cells, each said memory and reference cell comprising a left storage region for storing a first data bit as a level of electron charge and a right storage region for storing a second data bit as a level of electron charge, each said storage region comprising either a low programmed state (a data bit 0) wherein said electron charge is stored in said storage region or a high programmed state (a data bit 1) wherein no said electron charge is stored in said storage region, wherein each said cell has four possible data states 00, 01, 10, and 11, said method comprising.the steps of: (a) programming said reference cells according to a plurality of programming parameters, wherein said first and second data bits of said selected programmed memory cell are determined by reading said first and second data bits of said programmed reference cells; (b) selecting one of the said memory cells to read and determine said selected memory cell's data; (c) reading said left bit of said selected memory cell and generating a left bit output signal; (d) comparing said left bit output signal to at least one reference cell output signal to determine said memory cell data; (e) reading said right bit of said selected memory cell and generating a right bit output signal; (f) comparing said left bit output signal to at least one reference cell output signal to determine said memory cell data; and (g) determining if at least one other said memory cell should be read, and if so repeating steps (b) through (f).
In one embodiment of the present invention, the method is implemented using two corresponding reference cells to determine the data stored in one programmed memory cell. In another embodiment of the present invention, the method is implemented using three corresponding reference cells to determine the data stored in one programmed memory cell.
A key advantage of the method of reading dual-bit memory cells according to the present invention is more accurate memory cell reading over the life of the memory device.
The present invention also provides for a y-decoder architecture used to read the dual-bit memory cell
Fujitsu Limited
Phan Trong
Sheppard Mullin Richter & Hampton LLP
LandOfFree
Method and device for reading dual bit memory cells using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and device for reading dual bit memory cells using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and device for reading dual bit memory cells using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3095081