Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-12-20
2003-12-16
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06664943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a digital/analog converter circuit and a liquid crystal display (LCD) incorporating the digital/analog converter circuit and relates in particular to a so-called drive-circuit-integrated liquid crystal display in which a reference voltage selector type digital/analog converter circuit and a drive circuit containing this digital/analog converter circuit are integrally formed on a substrate on which polysilicon thin film transistors are arrayed in a matrix as switching devices for the pixels.
This invention also relates to a level shift circuit, a shift register using this level shift circuit and a liquid crystal display device incorporating this level shift circuit and shift register, and relates in particular to a level shift circuit having a basic structure comprised of CMOS latch cells, a shift register utilizing this level shift circuit in each level shift of the clock signal at each transfer stage, and a so-called drive-circuit-integrated liquid crystal display incorporating this level shift circuit or shift register as a circuit to configure the scanning circuit.
This invention also relates to a sampling latch circuit, a latch circuit and a liquid crystal display (LCD) incorporating the latch circuit and relates in particular to a sampling latch circuit having a level shift function and a basic structure comprised of CMOS latch cells, a latch circuit and a so-called drive circuit-integrated liquid crystal display device incorporating the sampling circuit and the latch circuit as circuits to configure the scanning circuit.
2. Description of the Related Art
A digital interface drive circuit integrated onto the same substrate as the pixel section by thin film transistors (TFT) and comprising a drive-circuit-integrated liquid crystal display of the related art is shown in FIG.
34
. First and a second horizontal drives
702
,
703
are mounted above and below an effective pixel region
701
arrayed with pixels in a matrix, and for instance, a vertical drive system
704
is installed on the left side in FIG.
34
and integrated onto the same substrate (hereafter called LCD panel) along with the effective pixel region
701
of thin film transistors.
The first horizontal drive
702
is comprised of a horizontal shift register
721
, a sampling & first latch circuit
722
, a second latch circuit
723
and a DA (digital/analog) converter circuit
724
. The second horizontal drive
703
is comprised, the same as the first horizontal drive
702
of a horizontal shift register
731
, sampling & first latch circuit
732
, a second latch circuit
733
and a DA (digital/analog) converter circuit
734
. The vertical drive system
704
is comprised of a vertical shift register
741
.
A significant problem that occurs when the above described drive circuit/liquid crystal display device of the related art is fabricated is the size of the surface area forming the drive circuit on the LCD panel or in other words, the peripheral area (hereafter called the picture frame) of the effective pixel region
701
. The circuit surface area of the DA converter circuits
724
,
734
is particularly important because the size of the LCD panel picture frame is determined by these DA converter circuits
724
,
734
area. A reference voltage selector type is widely utilized as the DA converter circuit for the drive-circuit-integrated liquid crystal display. The reason being that the reference voltage selector type has less variation in terms of output voltage potential.
The circuit structure of a reference voltage selector type DA converter circuit is shown in FIG.
35
. This circuit shows a 3-bit 8-step DA converter structure. In this DA converter-circuit as clearly shown in
FIG. 35
, step selector units
708
-
0
through
708
-
7
comprising a selector circuit
705
, latch circuit
706
and decode circuit
707
are formed for each step (reference voltages Vref F
0
through Vref
7
).
However, in the structure shown for the DA converter structure, since a latch circuit
706
and decoder circuit
707
are formed for each step, as clearly shown in the circuit structure of
FIG. 35
, an extremely large number of elements comprises the circuit so that when attempting to form a multi-step DA converter circuit of TFT components, the surface area of the circuit becomes extremely large. Consequently, when mounting the converter circuit on the liquid crystal display device, the LCD panel picture frame size is large, creating the problem that the overall device cannot be made compact.
A method was proposed for a circuit structure combining the reference voltage selector type DA converter circuit with a switching capacitor in order to reduce the size of the circuit surface area. However, this circuit structure required a buffer circuit so that the current consumption required just by the buffer circuit created the problem of a large increase in overall circuit power consumption.
An example of a level shift circuit comprised of CMOS devices is shown in the related art 1 in FIG.
13
A. In the level shift circuit of this related art 1, a CMOS latch cell
101
A has a basic structure comprised of an N channel MOS (hereafter simply NMOS) transistor Qn
101
A with a source connected to ground and a gate supplied by an input signal in
1
, an NMOS transistor Qn
102
A with a source connected to ground and a gate supplied with an input signal in
2
, a P channel MOS (hereafter simply PMOS) transistor Qp
101
A connected between power supply VDD and drain of NMOS transistor Qn
101
A with a gate connected to the drain of NMOS transistor Qn
102
A, a PMOS transistor Qp
101
A connected between the drain of NMOS transistor Qn
102
A and power supply VDD with a gate connected to the drain of the NMOS transistor Qn
101
A.
In the level shift circuit of the related art 1 for instance, a low voltage amplitude signal of 3 volts is input as signal in
1
, and a signal in
2
is input as an inverted signal of in
1
. These low voltage amplitude three volt input signals in
1
and in
2
appear in the drains of the NMOS transistors Qn
101
A, Qn
102
A as the amplitude of the power supply VDD circuit. The respective drain outputs of the NMOS transistors Qn
101
A, Qn
102
A are output as an inverted output signal xout by way of the inverter
103
A and an output signal out by way of the inverter
102
A. In this way, the low voltage amplitude signals in
1
, in
2
are level-shifted to a high voltage amplitude signal out and xout of the power supply VDD.
A level shift circuit of the related art 2 is shown in FIG.
14
A. In the level shift circuit of this related art 2, a CMOS latch cell
201
A has a differential amplifier structure comprised of a an N channel MOS (hereafter simply NMOS ) transistor Qn
201
A with a source connected to ground and a gate supplied by an input signal in
1
, an NMOS transistor Qn
202
A with a source connected to ground and a gate supplied with an input signal in
2
, a diode-connected P channel MOS transistor Qp
201
A connected between power supply VDD and drain of NMOS transistor Qn
201
A, and a PMOS transistor Qp
202
A connected between the drain of NMOS transistor Qn
202
A and power supply VDD and sharing a common gate with the NMOS transistor Qp
201
A.
In the level shift circuit of the related art 2 for instance, a low voltage amplitude signal of 3 volts is input as signal in
1
, and a signal in
2
is input as an inverted signal of in
1
. This low voltage amplitude three volt input signal in
1
appears in the drains of the NMOS transistors Qn
202
A as the amplitude of the power supply VDD circuit. The drain output of the NMOS transistor Qn
202
A is output as an output signal out by way of the inverter
202
A. In this way, the low voltage amplitude signal in
1
is level-shifted to a high voltage amplitude signal out of the power supply VDD.
However, in the above level shift circuits of the related art 1 and 2, a voltage sufficient to turn on the NMOS transistors Qn
101
A, Qn
201
A or the NMOS transistors Qn
102
A, Qp
202
A is required as the amplitude
Maekawa Toshikazu
Nakajima Yoshiharu
Kananen Ronald P.
Wu Xiao
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