Registers – Records – Conductive
Reexamination Certificate
2001-03-16
2003-06-24
St.Cyr, Daniel (Department: 2876)
Registers
Records
Conductive
C235S380000, C235S487000
Reexamination Certificate
active
06581843
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a record medium and a data transferring method using a nonvolatile memory suitable for an IC card having a flash memory suitable for storing music data and picture data, in particular, to those that allow a data transfer rate against a host device to be improved and a circuit scale to be reduced.
2. Description of the Related Art
As a storage device that stores music data and picture data disclosed in for example Japanese Patent Laid Open Publication No. 7-311708, an IC card having a flash memory is becoming attractive. The flash memory is a nonvolatile memory that is composed of memory cell transistors each of which has a floating gate. Such an IC card comprises a memory cell array, a controller, an interface packaged in a card shaped case. The controller controls read/write processes for data from/to the memory cell array. The interface inputs and outputs data to/from a host side device. When data is transferred to the host device, CRC (Cyclic Redundancy Code) is added to the data so as to correctly transfer data to the host device and detect an error. In a NAND type flash memory, data is accessed page by page. Thus, CRC code is generated page by page. When an error is detected using the CRC code, the data re-transfer process is performed.
In
FIG. 1
, reference numeral
101
is an IC card. Reference numeral
102
is a host device. The IC card
101
comprises a NAND type flash memory cell array. Examples of the host device
102
are a personal computer, a digital camera, a digital audio player, and a portable terminal unit. The host device
102
and the IC card
101
are connected through a transfer path
103
.
The host device
102
may have a card holding portion. By attaching the IC card
101
to the card holding portion, the IC card
101
is connected to the host device
102
. Alternatively, a drive device for the IC card
101
may be disposed. In this case, the IC card
101
is attached to the drive device. The host device
102
is connected to the IC card
101
through the drive device using a cable or a radio wave.
As shown in
FIG. 2
, the IC card
101
comprises a memory cell array
111
, a controller
112
, and an interface
113
. The controller
112
controls the read process of the memory cell array
111
. The interface
113
inputs and outputs data to/from the host side device. A data latch
115
is disposed in association with the memory cell array
111
. The controller
112
comprises a shift register
116
and a CRC calculating circuit
117
. The shift register
116
has a storage capacity for data of one page.
As shown in
FIG. 3
, the memory cell array
111
is composed of NAND strings. Each NAND string is composed of memory cell transistors each having a floating gate. For example, each NAND string is composed of for example 16 memory cell transistors MT
0
to MT
15
that are tandem connected and selection gate transistors SG
1
and SG
2
are connected to the drain side and the source side of the memory cell transistors MT
0
to MT
15
, respectively.
The drains of the drain side selection gate transistors SG
1
, SG
1
, and so forth are connected to bit lines BL
1
, BL
2
, and so forth, respectively. The sources of the source side selection gate transistors SG
2
, SG
2
, and so forth are connected to a source line Vs.
The gates of the memory cell transistors disposed in the line direction are connected to common word lines WL
0
, WL
1
, and W
15
, respectively. The gate of the selection gate transistor SG
1
is connected to a control signal line DSG. The gate of the selection gate transistor SG
2
is connected to a control signal line SSG. The word lines WL
0
to WL
15
and the control signal lines DSG and SSG are connected to row decoders (not shown). Memory cell transistors connected to the same word lines WL
0
, WL
1
, and WL
15
compose a page. The bit lines BL
1
, BL
2
, and so forth are connected to the data latch
115
.
In
FIG. 2
, when data that is read from the IC card
101
is transferred to the host device
102
side, data for one page is accessed from the memory cell array
111
of the IC card
101
. The data for one page is latched to the data latch
115
. The data for one page is transferred to the shift register
116
for a data re-transfer process for data to the host device
102
in the case that a transfer error takes place.
The data transferred to the shift register
116
is sent to the host device
102
side through the CRC calculating circuit
117
, the interface
113
, and the transfer path
103
. The data is sent from an interface
123
on the host device
102
side to the memory
124
through a CRC calculating circuit
122
and a data bus
125
.
When the data for one page is transferred from the IC card
101
to the host device
102
, the CRC code generated in the CRC calculating circuit
117
is sent to the host device
102
side.
The CRC calculating circuit
122
on the host device
102
side performs a CRC calculation using the received data and the CRC code and determines whether an error of the received data takes place. When the CRC calculating circuit
122
does not detect an error of the received data, as described above, data for the next page is read from the memory cell array
111
and transferred from the IC card
101
to the host device
102
.
When an error is detected, the host device
102
sends a data re-transfer request to the IC card
101
.
When the IC card
101
receives the data re-transfer request, the IC card
101
performs the data re-transfer process. In the data re-transfer process, data for one page stored in the shift register
116
is transferred to the host device
102
side through the transfer path
103
. After the data for one page has been transferred, the CRC code generated in the CRC calculating circuit
117
is sent to the host device
102
side.
The CRC calculating circuit
122
on the host device
102
side performs the CRC calculation using the received data and the CRC code and determines whether or not an error of the received data takes place. When the CRC calculating circuit
122
does not detect an error of the received data, as described above, data for the next page is read from the memory cell array
111
and transferred from the IC card
101
to the host device
102
FIGS. 4A
to
4
D and
5
A to
5
D are timing charts showing data transferred from the IC card
101
to the host device
102
.
FIGS. 4A
to
4
D show the operation in the case that a transfer error does not take place.
FIGS. 5A
to
5
D show the operation in the case that a transfer error takes place.
First of all, the operation in the case that a transfer error does not take place will be described.
In
FIG. 4A
, a signal RD is a signal that is internally generated corresponding to a read instruction to the memory cell array
111
. The signal RD causes a first access operation to be active. This instruction causes data for one page to be read from the memory cell array
111
and latched to the data latch
115
.
As shown in
FIG. 4A
, from time tg
00
to time tg
01
, the signal level of the signal RD becomes high. As a result, data D
0
for one page is read from the memory cell array
111
. As shown in
FIG. 4B
, at time tg
01
, the data D
0
is latched to the data latch
115
.
From time tg
01
to time tg
02
, the data D
0
is transferred from the data latch
115
to the shift register
116
.
From time tg
02
to time tg
04
, the data D
0
is transferred from the shift register
116
to the host device
102
. After the data D
0
for one page has been transferred, the CRC code is generated in the CRC calculating circuit
117
. The CRC code is transferred to the host device
102
side.
In addition, from time tg
02
to time tg
03
, the signal level of the signal RD becomes high. As a result, data for the next page is read from the memory cell array
111
. At time tg
03
, the data D
1
is latched to the data latch
115
.
At time tg
04
, the data D
0
for one page has been transferred. After the CRC code has been transferred, the CRC calculati
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
St.Cyr Daniel
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