Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-06-26
2003-07-22
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
C438S007000
Reexamination Certificate
active
06596553
ABSTRACT:
FIELD OF THE INVENTION
The present disclosure relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present disclosure relates to a method of pinhole decoration and detection.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS).
In the fabrication of devices on a wafer substrate, such as silicon, to form an IC, various metal layers and insulation layers can be deposited thereon. Insulation layers, such as, silicon dioxide, silicon oxynitride, fluorinated silicate glass (FSG), and spin-on glass (SOG) can provide electrical insulation between metal layers. The insulation layers can be protective layers or gap filling layers to achieve planarization in the wafer substrate. Insulation layers can be deposited by conventional technique such as plasma enhanced chemical vapor deposition (PECVD) and atmospheric pressure CVD.
Conventionally, a first level metal layer is separated by one or more insulation layers from a second level metal layer. This second level metal layer may be separated by one or more further insulation layers from a third level metal layer. These metal layers can be interconnected by metallization through vias or small holes or apertures etched in the intervening insulation layers.
In order to interconnect stacked layers, the stacked layers undergo photolithographic processing to provide a pattern and form vias. The top layer on the wafer substrate is covered with a photoresist layer of photo-reactive polymeric material for patterning via a mask. Light, such as, visible or ultraviolet (UV) light is directed through the mask onto the photoresist layer to expose it in the mask pattern. The polymeric material of the photoresist layer is transparent to the light yet photo-reactive to change its chemical properties, thereby permitting its patterning.
An antireflective coating (ARC) layer such as an organic ARC layer, can be provided at the top portion of the wafer substrate to minimize reflection of light back to the photoresist layer for more uniform patterning.
The photoresist may be of negative or positive type. In a negative photoresist, the exposed (polymerized) areas become insoluble while the unexposed (unpolymerized) areas dissolve in a later applied developer liquid. In a positive photoresist, the exposed (degraded) soluble areas dissolve in the developer liquid while the unexposed (insoluble) areas remain. In both instances, the photoresist material remaining on the wafer substrate forms the pattern to serve as a mask for etching in turn of the pertinent layers.
Etching processes are selective to particular types of materials with respect to other types of materials. For example, when etching via holes through a dielectric material, the etching process is selective to the dielectric material with respect to layers underlying the dielectric material. Generally, it is desirable to use anisotropic etching processes (etching processes with a high rate vertical direction etching and low rate or inhibited horizontal direction etching). Anisotropic etching processes are distinguished from isotropic etching processes (processes that etch the exposed surfaces equally in all directions). Anistropic etching processes generally attempt to provide an etched structure of uniform vertical wall geometry or profile. Etching processes can be manifested as wet etching (solution) or dry etching (plasma etching or reactive ion etching) techniques, depending on the physical and chemical characteristics of the material being etched and of the neighboring material.
For maximizing the integration (connection) of device components in the available area on the wafer substrate to fit more components in the same area, increasing miniaturization is required. As narrower metal lines and closer pitch dimensions are needed to achieve increasingly dense packing of the components, they become more vulnerable to defects at the minute tolerances involved. This has become apparent as IC miniaturization has increased to very large scale integration (VLSI) at sub-quarter micron and smaller dimensions.
Contaminants that are incompatible with the photo-reactive material can migrate into the photoresist layer from the ARC layer or other layer. These contaminants can poison the photoresist layer, causing non-uniformity of the reaction therein by extraneous chemical interaction with the polymeric material. This phenomenon is commonly called “photoresist poisoning” and leads to the formation of a photoresist footing where a positive photoresist is used, or to a photoresist pinching where a negative photoresist is used.
A disadvantage of common ARC layers (e.g., silicon oxynitride films) lies in their incompatibility with modern DUV (deep UV) photoresist systems due to reactive contaminants that are present therein. These reactive nitrogen substances tend to migrate or diffuse out of the silicon oxynitride layer and chemically interact with constituents of the photoresist layer.
As earlier above, such chemical interaction, commonly called photoresist poisoning, leads to photoresist footing or photoresist pinching. The photoresist footing or photoresist pinching problem leads to imperfect transfer of the photoresist pattern to the underlying substrate and ultimately limits the minimum spatial resolution of IC components.
Small holes or “pinholes” in insulating layers, such as silicon oxide nitride (SiON), can serve to facilitate resist poisoning. Accordingly, detecting pinholes early in development is important. Nevertheless, some pinholes are too small for many conventional state-of-the-art defect inspection tools to capture. Further, in the effort to make smaller and smaller transistors, the effects of small defects (e.g., small pinholes) increase in importance.
A variety of techniques exist for inspecting the surface of semiconductor wafers. These techniques include light scattering topography (LST), stylus profilometry, phase shift interferometry, and atomic force microscopy (FM). However, surface defects, such as pinholes, are not always detectable using conventional inspection devices and techniques.
Thus, there is a need to be able to enlarge and decorate small pinholes that are smaller than the inspection tool limit. Further, there is a need to capture pinholes. Even further, there is a need to more readily detect small pinholes. Yet further, there is a need for a method of inspecting a wafer to identify the presence of small pinholes.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of pinhole decoration and detection. The method can include providing a material layer above an amorphous carbon layer, providing a film over the material layer, and detecting a the pinhole. The material layer has a pinhole and a substantially planar surface except above the pinhole. The pinhole is detected by detecting a non-planar location on the substantially planar surface of the film.
Another exemplary embodiment relates to a method of detecting a pinhole in a layer of SiON to facilitate the prevention of resist poisoning. The method can include providing a SiON layer above an amorphous carbon layer where the SiON layer has a pinhole, providing a material over the SiON layer, and detecting the pinhole by detecting a location indicated by the material.
Another exemplary embodiment relates to a method of decorating and detecting a pinhole having a width smaller than detection tool limits. The method can include providing an amorphous carbon layer above a substrate, providing a reflective layer above the amorphous carbon layer, introducing a detection-assisting layer above the reflective layer to facilitate detection of a pinhole in the reflective layer, and detecting the pinhole.
REFERENCES:
patent: 5271796 (1993-12-01), Miyashita et al.
patent: 6162735 (2000-12-01), Zimmermann et al.
patent: 6225137 (2001-05-01), Lin
Bell Scott A.
Dakshina-Murthy Srikanteswara
Fisher Philip A.
Lin David
Advanced Micro Devices , Inc.
Cuneo Kamand
Sarkar Asok Kumar
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