Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-12-20
2003-09-09
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
C713S400000, C713S503000
Reexamination Certificate
active
06618457
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device for receiving an external data signal to generate an internal data signal in a high speed memory device; and, more particularly, to an apparatus and method for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of rising and falling edges of a main clock.
DESCRIPTION OF THE PRIOR ART
Recently, synchronous dynamic random access memory (hereinafter, referred to as SDRAM) is widely used in order to obtain a high speed of operation. The SDRAM is performed in synchronization with an external clock signal, for example, a system clock. While a single data rate (SDR) SDRAM as one kind of the SDRAM employs a rising of the external clock signal, a double data rate (DDR) SDRAM as another kind of the SDRAM employs both a falling of the external clock signal and a rising thereof. That is, data write/read operations of the DDR SDRAM is performed in synchronization with the rising and falling edges of the external clock signal, so that the DDR SDRAM operates at a high speed.
In the prior art, since the conventional DRAM such as the SDR SDRAM receives the data signal in synchronization with only one of both edges of the clock signal, a data mask buffer or a data input buffer can be implemented with a dynamic buffer or a static buffer without any circuit modification. However, since the high-speed memory device such as the DDR SDRAM which receives the data signal in synchronization with rising and falling edges of the clock signal needs a different buffer circuit from the prior art.
At this time, while each data signal is inputted at every half period interval, a core circuit of the DDR SDRAM processes the data signal at one period of the clock like the SDR SDRAM. That is, the DDR SDRAM receives the external data signal in synchronization with the rising and falling edges of the clock signal and generates two internal data signal in synchronization with one of both edges of the clock signal.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock.
It is, therefore, another object of the present invention to provide a method for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock.
In accordance with an aspect of the present invention, there is provided a method for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock in a high speed memory device, comprising the steps of: a) receiving the external signal to generate a full-swing level signal; b) dividing the full-swing level signal into a first signal and a second signal in synchronization with the data strobe signal, wherein the first signal is activated in synchronization with rising edges of the data strobe signal and the second signal is activated in synchronization with falling edges of the data strobe signal; c) aligning the first signal and the second signal with one of both edges of the data strobe signal; and d) aligning the aligned first and second signals with one of both edges of the main clock.
In accordance with another aspect of the present invention, there is provided an apparatus for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock in a high speed memory device, comprising: a) a means for comparing a reference voltage signal with the external signal to generate a full-swing level signal; b) a first signal generating means for receiving the full-swing level signal and an inverted full-swing level signal to generate a first signal in synchronization with a first strobe signal, wherein the first strobe signal is synchronized with one edge of the data strobe signal; c) a second signal generating means for receiving the full-swing level signal and the inverted full-swing level signal to generating a second signal in synchronization with a second strobe signal, wherein the second strobe signal is synchronized with the other edge of the data strobe signal; d) a first align means for latching and outputting the first signal in response to the second strobe signal, so that the first and second signals are aligned with a same point of the data strobe signal; and e) a second align means for latching the output signal of the first align means and the second signal to generate two internal signals in synchronization with a third strobe signal, wherein the third strobe signal is a signal synchronized with one edge of the main clock, whereby the output signals of the second align means are aligned with the main clock.
REFERENCES:
patent: 6401213 (2002-06-01), Jeddeloh
patent: 6466491 (2002-10-01), Yanagawa
Yi Seung-Hyun
Yun Mi-Kyung
Blakely & Sokoloff, Taylor & Zafman
Hyundai Electronics Industries Co,. Ltd.
Vo Don N.
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