Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
2001-09-25
2003-09-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S137000, C438S138000, C257S133000, C257S137000
Reexamination Certificate
active
06620653
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-297698, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND
The present invention relates to a high voltage semiconductor device, and more particularly, to a power device such as an IGBT.
A conventional high voltage vertical power device will be explained below while taking the case of a punch through type IGBT using an epitaxial substrate.
FIG. 1
is a sectional view of a cell area of the conventional punch through type IGBT using the epitaxial substrate.
The epitaxial substrate comprises a positive semiconductor substrate (positive collector layer)
11
and a negative epitaxial layer formed on the semiconductor substrate
11
by an epitaxial growth method. In this example, the epitaxial layer comprises a negative buffer layer
12
and a N type drift layer (active layer)
13
. For example, concentration of positive impurity in the semiconductor substrate
11
is set to about 7.5×10
18
atoms/cm
3
, concentration in the negative impurity in the buffer layer
12
is set to about 2.7×10
17
atoms/cm
3
, and concentration of negative impurity in the drift layer
13
is set to about 1.35×10
14
atoms/cm
3
.
A positive base layer
14
is formed on a surface region of the drift layer
13
. A negative emitter layer
15
and a positive base contact layer
16
are formed in the positive base layer
14
. A negative low resistant layer
17
which is adjacent to the positive base layer
14
is formed in the drift layer
13
.
For example, surface concentration of positive impurity in the positive base layer
14
is set to about 4.0×10
17
atoms/cm
3
, surface concentration of negative impurity in the negative emitter layer
15
is set to about 1.27×10
20
atoms/cm
3
, surface concentration of positive impurity in the positive base contact layer
16
is set to about 2.8×10
19
atoms/cm
3
, and surface concentration of negative impurity in the negative low resistant layer
17
is set to about 5.0×10
15
atoms/cm
3
.
An emitter electrode
18
is formed on the negative emitter layer
15
and the positive base contact layer
16
. The emitter electrode
18
is in contact with the negative emitter layer
15
and the positive base contact layer
16
. A gate electrode
20
is formed on the positive base layer
14
through an insulating film
19
. A collector electrode
21
is formed on a back surface of the semiconductor substrate
11
.
In the conventional power device including the above-described IGBT, an epitaxial substrate is employed. However, manufacturing cost of the epitaxial substrate is high and as a result, a cost of the vertical power device is increased.
In the power device, a so-called life time control is conducted in order to enhance the turn off characteristics. As the life time is shorter, a high speed turn off is possible. Therefore, the life time has been set from a range of 5 to 10 &mgr;s to about 100 ns.
However, as is well known, the turn off characteristics and the on characteristics are in a relation of trade-off. That is, if the turn off characteristics is enhanced, ON voltage becomes higher and on characteristics are deteriorated.
This trade-off relation is generated not only in the above-described punch through type device having the buffer layer, but also in a non-punch through type device having no buffer layer and in a trench gate type device.
SUMMARY
Semiconductor devices according to first and second aspects of inventions comprise: a first conductive type first base layer; a second conductive type collector layer on a side of a first surface of the first base layer; a first conductive type buffer layer between the first base layer and the collector layer; a second conductive type second base layer on a side of a second surface of the first base layer; a first conductive type emitter layer in the second base layer; and a gate electrode above the second base layer between the emitter layer and the first base layer.
In the semiconductor device of the first aspect of the invention, the first base layer may comprise a semiconductor substrate, each of the collector layer, the second base layer and the emitter layer comprises a diffusion layer in the semiconductor substrate, and a depth of diffusion of the collector layer is 1 &mgr;m or less.
In the semiconductor device of the second aspect of the invention, the following condition may be satisfied: 5≧bDP·QP/bDN·QN (QN is a dose amount of the buffer layer, bDN is an average of a diffusion coefficient in the buffer layer, QP is a dose amount of the collector layer, and bDP is an average of a diffusion coefficient in the collector layer).
A manufacturing method of a third aspect of a invention is applied to a semiconductor device in which a power device and its control section are formed in one chip, and comprises a step for implanting impurities into a forming region of the power device and a forming region of the control section at the same time, thereby forming a first impurity layer which becomes a portion of the power device in the forming region of the power device, and a step for forming a second impurity layer which becomes a portion of the control element in the forming region of the control section.
A manufacturing method of a fourth aspect of a invention is applied to a semiconductor device in which a power device and its control section is formed in one chip, and comprises: a step for forming a conductive film in each of a forming region of a power device and a forming region of a control section, a step for etching the conductive films by RIB using one mask, a step for forming a first electrode which becomes a portion of the power device in the forming region of the power device, and a step for forming a second electrode which becomes a portion of the control element in the forming region of the control section.
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S. Dewar, et al. “Soft Punch Through (SPT)-Setting new Standards in 1200V IGBT” Power Conversion, Jun. 2000 Proceedings, pp. 593-600.
T. Laska, et al. “TheFieldStop IGBT (FS IGBT)-A New Power Device Concept with a Great Improvement Potential” IEEE International Symposium on Power Semiconductor Devices & ICs 2000 pp. 355-358.
F. Auerbach, et al. “6,5kV IGBT-Modules” International Power Electronics Conference, IPEC-Tokyo 2000 pp. 275-279.
Tomoko Matsudai, et al. “New 600 V Trench Gate Punch-Through IGBT Concept with Very Thin Wafer and Low Efficiency p-emitter, having an On-state Voltage Drop lower than Diodes” International Power Electronics Conference IPEC-Tokyo 2000 pp. 292-296.
F . Bauer et al., “Design Considerations and Characteristics of Rugged Punchthrough (PT) IGBTs with 4.5kV Blocking Capability”, IEEE 1996, pp. 327-330.
S. Dewar, et al. “Soft Punch Through (SPT)-Setting new Standards in 1200V IGBT” Power Conversion, Jun. 2000 Proceedings, pp. 593-600.
T. Laska, et al. “TheFieldStop IGBT (FS IGBT)-A New Power Device Concept with a Great Improvement Potential” IEEE International Symposium on Power Semiconductor Devices & ICs 2000 pp. 355-358.
F. Auerbach, et al. “6,5kV IGBT-Modules” International Power Electronics Conference, IPEC-Tokyo 2000 pp. 275-279.
Tomoko Matsudai, et al. “New 600 V Trench Gate Punch-Through IGBT Concept with Very Thin Wafer and Low Efficiency p-emitter, having an On-state Voltage Drop lower than Diodes” International Power Electronics Conference IPEC-Tokyo 2000 pp. 292-296.
Hattori Hidetaka
Matsudai Tomoko
Nakagawa Akio
Kabushiki Kaisha Toshiba
Lindsay Jr. Walter L.
Niebling John F.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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