Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-11-17
2003-09-09
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S099000, C345S100000, C345S182000, C345S440000, C345S581000, C348S580000, C348S581000, C348S582000, C348S583000
Reexamination Certificate
active
06618032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display apparatus. More particularly, the present invention relates to a picture display apparatus which has the function of displaying a video signal with a number of vertical pixels different from the number of vertical pixels of a display unit of the picture display apparatus as an enlarged or thinned picture.
2. Description of the Related Art
Typically, in a picture display apparatus for a personal computer, the number of pixels on a display panel is prescribed by specifications such as VGA specifications, SVGA specifications, XGA specifications, SXGA specifications and UXGA specifications where VGA, SVGA, XGA, SXGA and UXGA are IBM's registered trademarks indicating commonly known representative specifications. In some cases, however, the number of pixels of a video signal supplied to a picture display apparatus may be different from the number of pixels on a display panel of the apparatus. For example, a picture conveyed by a VGA video signal is displayed on a display panel conforming to the XGA specifications. In such a case, it is necessary to display the video signal on the display panel as an enlarged or thinned picture.
When a video signal is displayed in the conventional system as a picture enlarged in the vertical direction, for example, data to be displayed on the area as an enlarged picture is stored in a memory and the data is then written onto a plurality of lines on the picture display apparatus. In this conventional system, however, peripheral components such as the memory and an A/D converter are required, making the picture display apparatus large in size and complicated. In order to solve this problem, there has been proposed the following method of displaying a video signal on a display panel as an enlarged picture without employing such peripheral components.
In a picture display apparatus having a function of displaying a video signal on a display panel thereof as an enlarged picture, a mode signal is set in a gate driver to indicate whether a video signal is to be displayed on the display panel normally or as an enlarged picture. During a horizontal period for outputting picture data of a line, driving of a gate line and driving of a plurality of gate lines are switched from one to another in dependence on the type of the mode signal. A gate line driven during a horizontal period will result in a normal display. On the other hand, a plurality of gate lines driven at the same time during a horizontal period will display picture data of a line on the same plurality of lines on the display screen, resulting in a display enlarged in the vertical direction.
FIG. 8
is a timing diagram showing the operation of a gate driver employed in the picture display apparatus.
FIG. 8A
is a timing diagram for the normal mode while
FIG. 8B
is a timing diagram for an enlarge mode with a multiplication factor of two. As shown in
FIG. 8B
, gate output waveforms on two adjacent lines, namely X
1
and X
2
or X
3
and X
4
, are generated at the same time.
In equipment such as a liquid-crystal display apparatus, there is generally adopted a technique whereby a supplementary capacitor is added to each pixel to hold electric charge during each scanning period. As a technique to lower the numerical aperture without using a capacitive electrode for forming a supplementary capacitor, a pixel electrode and a gate line are put in an overlapping layout to form a structure of a supplementary capacitor known as the so-called Cs on-gate structure. That is, the supplementary capacitor has a configuration comprising the pixel electrode and the gate line.
However, the enlarged-picture display technology can not be applied to a liquid-crystal display apparatus provided with supplementary capacitors each having the Cs on-gate structure. This is because, in the Cs on-gate structure, a gate line adjacent to a gate line driving a pixel serves as one of the electrodes of a supplementary capacitor of the pixel so that, when data is written into a pixel connected to one of the gate lines, that is, when the waveform output by the gate is set at a high level, the supplementary capacitor does not function unless the waveform output by a gate connected to the adjacent gate line is set at a low level. Since the technique to display an enlarged picture causes gates connected to two adjacent gate lines to output the same waveform, the supplementary capacitor does not function.
SUMMARY OF THE INVENTION
It is thus an object of the present invention addressing the problem to provide a display device which functions to display an enlarged picture and functions to display a shrunk (thinned) picture and is thus applicable to a picture display apparatus such as a liquid-crystal display apparatus provided with supplementary capacitors each having the Cs on-gate structure.
In order to achieve the object described above, the present invention provides a display apparatus that functions to display an enlarged picture. The display apparatus is characterized in that the apparatus is provided with a driving circuit having: a pulse generating means for generating second clock pulse signals to copy in a horizontal period in an operation to display a video signal having a vertical-pixel count smaller than a predetermined vertical-pixel count of a display unit as an enlarged picture on a screen of the display unit by using two kinds of fields in addition to as many original clock pulse signals as required in an operation to display a video signal having a vertical-pixel count equal to the predetermined vertical-pixel count of the display unit and for repeating generation of the original clock pulse signals and the second clock pulse signals for each horizontal period; a gate-clock generating means for receiving the original clock pulse signals and the second clock pulse signals from the pulse generating means and for generating gate-clock signals obtained as a result of superposing all of the original clock pulse signals on some of the second clock pulse signals wherein the number of the superposed second clock pulse signals is equal to a difference obtained as a result of subtraction of the vertical-pixel count of the video signal from the predetermined vertical-pixel count of the display unit and any adjacent two of the superposed second clock pulse signals pertain to the two kinds of fields separated from each other by at least two horizontal periods; and a gate driving means for receiving the gate clock signals from the gate-clock generating means and for generating gate driving signals used for driving as many gate lines as pulses of the gate clock signals for each horizontal period.
In a driving circuit employed in a display apparatus of the present invention having a function to display an enlarged picture, in the first place, a pulse generating means generates an original clock pulse signal and a second clock pulse signal for a copy purpose during a horizontal period. These clock pulse signals are generated repeatedly for each horizontal period. In order to generate gate clock signals having a number of pulses matching the vertical-pixel count of the display unit, the gate-clock generating means is used for generating gate-clock signals obtained as a result of superposing all of the original clock pulse signals on some of the second clock pulse signals wherein the number of the superposed second clock pulse signals is equal to a difference obtained as a result of subtraction of the vertical-pixel count of the video signal from a predetermined vertical-pixel count of the display unit. Then, the gate driving means receives the gate clock signals from the gate-clock generating means and generates a plurality of gate driving signals corresponding to pulses of the gate clock signals. The gate driving signals are generated with timings different from each other, being set at a high level for equal periods of time. It should be noted that a high-level period is a period between the rising edge of a pulse and the rising ed
Abdulselam Abbas
Alps Electric Co. ,Ltd.
Brinks Hofer Gilson & Lione
Hjerpe Richard
LandOfFree
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