Method of testing serial interface

Details Method of testing serial interface Method of testing serial interface

2001-07-13

2003-09-23

Wachsman, Hal (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S125000, C714S731000, C714S814000

Reexamination Certificate

active

06625560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of circuit testing and, in particular, to a method for testing a serial interface.
2. Description of Related Art
Automated test equipment (ATE) is frequently used to test electrical circuits.
FIG. 1A
shows a typical conventional testing configuration using automated test equipment. Assume for example that an integrated circuit having a transmitter section (TX)
12
for driving a serial interface is to be tested. Typically, the transmitter section
12
is connected to an interface receiver section (RX)
14
by a short cable
8
. The receiver section
14
is known to operate within specification and is thus sometimes referred to as a golden unit. The cable
8
includes at least one pair that carry a clock in differential form and at least one pair that carry data in differential form. Thus, the interface contains both data and clock information which are transmitted over separate lines. A clock derived from the clock information is used by the receiver section to sample the data information transmitted over the interface.
One section
10
A of automated test equipment is located at the transmitter section
12
and is used to generate the data and the clock information to be transmitted over the interface. Another section
10
B of automated test equipment is used to receive the detected data and compare the data with the data that was transmitted or some other form of reference data. If immunity to phase jitter is to be tested, the section
10
A test equipment operates to introduce a specified amount of phase jitter into the clock used to produce the clock information. By way of example, the jitter specification may be 1 ns peak-to-peak jitter at a 1 MHz jitter frequency.
FIGS. 2A
,
2
B and
2
C show a conventional technique of introducing phase jitter.
FIG. 2A
shows a signal, such as a clock, having a base period P
1
. Assume that a falling edge FE of the clock is used to clock or sample data received over an interface together with the clock. In order to simulate phase jitter, the falling edge of the clock is first advanced a fixed amount in time, +0.5 ns for example, as shown in FIG.
2
B. Next, as can be seen in
FIG. 2C
, the falling edge of the clock is then retarded a fixed amount in time, −0.5 ns for example. Typically, the falling edge is advanced in increments to reach the +0.5 ns point and then is incrementally returned to the original position. The clock is then retarded in increments to reach the −0.5 nanosecond point and then incrementally returned to the original position so that one complete cycle of 1 nanosecond of peak-to-peak jitter is produced.
Rather than having separate data and clock lines as shown in
FIG. 1A
, it is possible to recover the clock from the data channel. In that event, only the modulated data need be transmitted as shown in FIG.
1
B. Thus, both data and clock information are transmitted over the interface on common lines. Again, the above-described technique is used to introduce phase jitter onto the clock used to modulate the data to be transmitted by a transmitter section
15
. Well known circuitry is present at the receiver section
17
to recover the clock and to demodulate the received signal to obtain the data.
The prior art method of testing described above does posses certain shortcomings. First, this approach is limited with respect to the magnitude of the amount of phase jitter that can be introduced. The falling edge FE (
FIG. 2B
) can only be shifted a time period which corresponds to ±180 degrees. Further, such approach is not easily implemented using automated test equipment.
The present invention overcomes the above-noted limitations of the prior art. The magnitude of the phase jitter that can be introduced is essentially unlimited. Further, the method can be readily implemented using automated test equipment. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
SUMMARY OF THE INVENTION
A method of testing a circuit having an interface over which data and clock information are transmitted and where the data information is sampled using a clock derived from the clock information so as to produce sampled data is disclosed. Phase jitter is introduced on the clock which produces the clock information by increasing the period of the clock from a base period by a first increment period for a first predetermined number of clock cycles. By way of example, if the first increment period is 0.0625 ns and the first predetermined number of clock cycles is sixteen, the total phase shift will increase by 1 ns (16×0.0625 ns). The clock is also cycled by decreasing the period of the clock from the base period by a second increment period for a second predetermined number of clock cycles. As a further example, if the second increment period is 0.0625 ns and the second predetermined number of clock cycles is sixteen, the total phase shift will decrease by 1 ns. Preferably, the first and second predetermined number of clock cycles are both at least two.
As the clock is cycled though the first and second time periods, the circuit being tested is caused to sample the data using the clock derived from the clock information. The sampled data is then compared with reference data to determine if any errors occurred.


REFERENCES:
patent: 5309428 (1994-05-01), Copley et al.
patent: 5835501 (1998-11-01), Dalmia et al.
patent: 6076175 (2000-06-01), Drost et al.
patent: 6385236 (2002-05-01), Chen

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