Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
2000-12-18
2003-03-18
Wong, Edna (Department: 1741)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S098300, C427S299000, C205S118000, C205S123000, C205S210000, C205S104000, C205S291000, C205S239000, C205S137000
Reexamination Certificate
active
06534116
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor plating method and apparatus. More particularly, the present invention is directed to a method and apparatus that creates a differential between additive adsorbed on a top surface of a workpiece and additive adsorbed within a cavity portion of the workpiece using an external influence to enhance plating of a conductive material in the cavity portion of the workpiece.
BACKGROUND OF THE INVENTION
There are many steps required in manufacturing multi-level integrated circuits (IC). Such steps include depositing conductive and insulator materials on a semiconductor wafer or substrate followed by full or partly removal of these materials using photo-resist patterning, etching, and the like. After photolithography, patterning and etching steps, the resulting surface is generally non-planar as it contains many cavities or features such as vias, lines, trenches, channels, bond-pads, and the like that come in a wide variety of dimensions and shapes. These features are typically filled with a highly conductive metal material before additional processing steps such as etching and/or chemical mechanical polishing (CMP) is/are performed. Accordingly, a low resistance interconnection structure is formed between the various levels/sections of the IC.
Copper (Cu) is quickly becoming the preferred material for interconnections in ICs because of its low electrical resistively and high resistance to electro-migration. Electrodeposition is one of the most popular methods for depositing Cu into the features on the substrate surface.
As can be expected, there are many different designs of Cu plating systems that have been used in this industry. For example, U.S. Pat. No. 5,516,412 issued on May 14, 1996, to Andricacos et al. discloses a vertical paddle plating cell that is designed to electrodeposit a film on a flat article. Next, U.S. Pat. No. 5,985,123 issued on Nov. 16, 1999, to Koon discloses yet another vertical electroplating apparatus, which purports to overcome the non-uniform deposition problems associated with varying substrate sizes. Further, U.S. Patent No. 5,853,559 issued on Dec. 29, 1998, to Tamaki et al. discloses an electroplating apparatus that minimizes waste of the plating electrolyte and accomplishes high recovery of the electrolyte.
During the Cu electrodeposition process, specially formulated plating solutions or electrolyte are used. These solutions or electrolyte contain ionic species of Cu and additives to control the texture, morphology, and the plating behavior of the deposited material. Additives are needed to make the deposited layers smooth and somewhat shiny.
There are many types of Cu plating solution formulations, some of which are commercially available. One such formulation includes Cu-sulfate (CUSO
4
) as the copper source (see James Kelly et al., Journal of The Electrochemical Society, Vol. 146, pages 2540-2545, (1999)) and includes water, sulfuric acid (H
2
SO
4
), and a small amount of chloride ions. As is well known, other chemicals can be added to the Cu plating solution to achieve desired properties of the deposited material.
The additives in the Cu plating solution can be classified under several categories such as suppressors, levelers, brighteners, grain refiners, wetting agents, stress-reducing agents, accelerators, etc. In many instances, different classifications are often used to describe similar functions of these additives. Today, solutions used in electronic applications, particularly in manufacturing ICs, contain simpler additives consisting of two-component two-ingredient packages (e.g., see Robert Mikkola and Linlin Chen, “Investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistries used for Advanced Interconnect Metallization”, Proceedings of the International Interconnect Technology Conference, pages 117-119, Jun. 5-7, 2000). These formulations are generically known as suppressors and accelerators.
Suppressors are typically polymer formulated from polyethylene glycol-PEG or polypropylene glycol-PPG and is believed to attach themselves to the substrate surface at high current density regions, thereby forming a high resistance film and suppressing the material deposited thereon. Accelerators are typically organic disulfides that enhance Cu deposition on portions of the substrate surface where they are adsorbed. The interplay between these two additives and possibly the chloride ions determines the nature of the Cu deposit.
The following figures are used to more fully describe the conventional electrodeposition method and apparatus.
FIG. 1
illustrates a perspective view of a cross-section of a substrate
3
having an insulator
2
formed thereon. Using conventional etching techniques, features such as a row of small vias
4
a
and a wide trench
4
b
are formed on the insulator
2
and the substrate
3
. In this example, the vias
4
a
are narrow and deep; in other words, they have high aspect ratios (i.e., their depth to width ratio is large). Typically, the widths of the vias
4
a
are sub-micron. The trench
4
b
, on the other hand, is typically wide and has a small aspect ratio. In other words, the width of the trench
4
b
may be five to fifty times or more greater than its depth.
FIGS. 2
a
-
2
c
illustrate a conventional method for filling the features with Cu.
FIG. 2
a
illustrates a cross sectional view of the substrate
3
in
FIG. 1
having various layers disposed thereon. For example, this figure illustrates the substrate
3
and the insulator
2
having deposited thereon a barrier/glue or adhesion layer
5
and a seed layer
6
. The barrier layer
5
may be tantalum, nitrides of tantalum, titanium, tungsten, or TiW, etc., or combinations of any other materials that are commonly used in this field. The barrier layer
5
is generally deposited using any of the various sputtering methods, by chemical vapor deposition (CVD), or by electroless plating methods. Thereafter, the seed layer
6
is deposited over the barrier layer
5
. The seed layer
6
material may be copper or copper substitutes and may be deposited on the barrier layer
5
using various sputtering methods, CVD, or electroless deposition or combinations thereof.
In
FIG. 2
b
, after depositing the seed layer
6
, a conductive material
7
(e.g., copper layer) is generally electrodeposited thereon from a suitable acidic or non-acidic plating bath or bath formulation. During this step, an electrical contact is made to the Cu seed layer
6
and/or the barrier layer
5
so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the Cu material
7
is electrodeposited over the substrate surface using the specially formulated plating solutions, as discussed above. By adjusting the amounts of the additives, such as the chloride ions, suppressor/inhibitor, and the accelerator, it is possible to obtain bottom-up Cu film growth in the small features.
The Cu material
7
completely fills the via
4
a
and is generally uniform in the large trench
4
b
, but does not completely fill the trench
4
b
because the additives that are used are not operative in large features. For example, it is believed that the bottom up deposition into the via
4
a
occurs because the suppressor/inhibitor molecules attach themselves to the top of the via
4
a
to suppress the material growth thereabouts. These molecules can not effectively diffuse to the bottom surface of the via
4
a
through the narrow opening. Preferential adsorption of the accelerator on the bottom surface of the via
4
a
results in faster growth in that region, resulting in bottom-up growth and the Cu deposit profile as shown in
FIG. 2
b
. Without the appropriate additives, Cu can grow on the vertical walls as well as the bottom surface of the via
4
a
at the same rate, thereby causing defects such as seams and/or voids.
Adsorption characteristics of the suppressor and accelerator additives on the bottom surface of the large trench
4
b
is not ex
Nutool, Inc.
Pillsbury & Winthrop LLP
Wong Edna
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