Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1998-09-28
2003-04-15
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
Reexamination Certificate
active
06548828
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin-film transistor, for example, a bottom gate type thin-film transistor suitable for a pixel displaying switching element of an active matrix system display panel or the like and to a manufacturing method thereof.
2. Description of the Prior Art
FIG. 1
is a sectional view showing a structure of a bottom gate type thin-film transistor.
A gate electrode
2
constituted of a high-melting metal (refractory metal) such as tungsten, chromium, or the like is formed on a surface of an insulating transparent substrate
1
. The gate electrode
2
has opposite ends enlarged toward the transparent substrate
1
to form a tapered configuration. A silicon oxide film
4
is deposited via a silicon nitride film
3
on the transparent substrate
1
with the gate electrode
2
formed thereon. The silicon nitride film
3
inhibits impurities contained in the transparent substrate
1
from penetrating an active region described later, while the silicon oxide film
4
works as a gate insulating film. A polycrystalline silicon layer
5
is deposited on the silicon oxide film
4
in such a manner that the film
5
extends across the gate electrode
2
. The polycrystalline silicon layer
5
forms the active region of the thin-film transistor.
A stopper
6
formed of a silicon oxide or another insulating material is disposed on the polycrystalline silicon layer
5
. A portion of the polycrystalline silicon layer
5
covered with the stopper
6
forms a channel region
5
c
, and the other portions of the polycrystalline silicon layer
5
form a source region
5
s
and a drain region
5
d
. Laminated on the polycrystalline silicon layer
5
with the stopper
6
formed thereon are a silicon oxide film
7
and a silicon nitride film
8
. The silicon oxide film
7
and the silicon nitride film
8
construct an interlayer insulating film to protect the polycrystalline silicon layer
5
including the source region
5
s
and the drain region
5
d.
Contact holes
9
are formed at predetermined positions of the silicon oxide film
7
and the silicon nitride film
8
on the source region
5
s
and the drain region
5
d
. A source electrode
10
s
and a drain electrode
10
d
are disposed in the contact holes
9
, and connected to the source region
5
s
and the drain region
5
d
, respectively. An acrylic resin layer
11
transparent to visible light is formed on the silicon nitride film
8
with the source electrode
10
s
and the drain electrode
10
d
formed therein. The acrylic resin layer
11
fills in surface asperities generated by the gate electrode
2
and the stopper
6
to flatten a surface.
A contact hole
12
is formed in the acrylic resin layer
11
on the source electrode
10
s
. A transparent electrode
13
made of ITO (Indium Tin Oxide) or the like connected to the source electrode
10
s
via the contact hole
12
is disposed to spread over the acrylic resin layer
11
. The transparent electrode
13
constitutes a pixel electrode of a liquid crystal display panel.
A plurality of the aforementioned thin-film transistors are arranged together with the pixel electrodes in a matrix on the transparent substrate
1
, and apply to the pixel electrodes image data supplied to the drain electrodes
10
d
in response to a scanning control signal applied to the gate electrodes
2
.
Additionally, a crystal particle diameter of the polycrystalline silicon layer
5
is preferably formed to a sufficient size so that the film
5
functions as the active region of the thin-film transistor. As a method of forming the polycrystalline silicon layer
5
with a large crystal particle diameter, a laser annealing method using an excimer laser is known. In the laser annealing method, silicon in an amorphous state is formed on the silicon oxide film
4
constituting the gate insulating film, an excimer laser is irradiated to the silicon to temporarily melt the silicon, and the silicon is crystallized. When the laser annealing method is used, a temperature of the transparent substrate
1
does not need to be raised. Therefore, a low-melting glass substrate can be used as the transparent substrate
1
.
The silicon oxide film
4
forming the gate insulating film is formed to cross over a step generated by the gate electrode
2
. In this case, the gate electrode
2
has a section formed in a trapezoidal shape in such a manner that its side wall forms an acute angle with a surface of the transparent substrate
1
, but insulation defect of the gate insulating film easily occur in the stepped portion. This is because the silicon oxide film
4
formed in a plasma CVD process has a coarser or non-dense quality compared with a silicon oxide film formed by a high-temperature thermal oxidation processing, and even its slightly bent portion may not maintain withstanding voltage. Therefore, a problem arises that current leakage occurs between the gate electrode
2
and the active region which is polycrystalline silicon layer
5
, operating characteristics are deteriorated, and an inoperable state is caused in an extreme case.
SUMMARY OF THE INVENTION
An object of the present invention is to prevent insulation defects from arising in a gate insulating film.
To attain this and other objects, the present invention provides a thin-film transistor which comprises a gate electrode disposed on a substrate, a gate insulating film formed on the substrate to cover the gate electrode, a semiconductor film formed on the gate insulating film to cross over the gate electrode, and an interlayer insulating film formed on the semiconductor film. The gate electrode is expanded in width toward the substrate, and the gate insulating film is provided with a silicon oxide film having a thickness of at least 1200 Å.
Moreover, in another aspect of the present invention, a silicon nitride film having a thickness of at least 400 Å is formed between the substrate and the silicon oxide film.
According to another aspect of the present invention, a method of manufacturing a thin-film transistor includes a first step of forming a gate electrode on a main surface of a substrate, a second step of forming a gate insulating film on the substrate to cover the gate electrode, a third step of forming a semiconductor film on the gate insulating film to cross over the gate electrode, and a fourth step of forming an interlayer insulating film on the semiconductor film. In the first step, the gate electrode is expanded in width toward the substrate, and in the second step, the silicon oxide film is formed to a thickness of at least 1200 Å.
According to the present invention, since the silicon oxide film constituting the gate insulating film is formed in a thickness of 1200 Å or more, a stepped portion formed by the gate electrode is completely covered, and insulation defects of the gate insulating film can be reduced. Furthermore, since the silicon nitride film is formed in a thickness of 400 Åor more between the substrate and the silicon oxide film, deposition of impurities from the substrate is inhibited. Moreover, since the film is dense, the stepped portion formed by the gate electrode is moderated, and a flatter film surface is formed. Therefore, insulating strength (withstanding voltage) of the silicon oxide film formed in an upper layer can further be enhanced.
As aforementioned, according to the present invention, the withstanding voltage of the gate insulating film can be enhanced, and the current leakage between the gate electrode and the active region can be reduced. Therefore, not only manufacturing yield but also reliability can be improved.
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patent: 5162892 (1992-11-01), Hayashi et al.
patent: 5164805 (1992-11-01), Lee
patent: 5200846 (1993-04-01), Hiroki et al.
patent: 5296729 (1994-03-01), Yamanaka et al.
patent: 5440168 (1995-08-01), Nishimura et al.
patent: 5468986 (1995-11-01), Yamanashi
patent: 5534445 (1996-07-01), Tran et al.
patent: 5545576 (1996-08-01), Matsumoto et al.
patent: 56169
Nakanishi Shiro
Yoneda Kiyoshi
Abraham Fetsum
Cantor & Colburn LLP
Sanyo Electric Co,. Ltd.
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