Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2002-05-28

2003-09-23

Lam, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S230030

Reexamination Certificate

active

06625051

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to reduction of memory array noise in a semiconductor apparatus involving a memory array or arrays.
BACKGROUND OF THE INVENTION
The items of literature referenced in this specification are listed below, and they will be referenced by reference number. [Reference 1]: ITOH, K.,
Very Large Scale Integrated Memories
, Baifukan, Nov. 5, 1994 (1st edition), pp. 214-217, and [Reference 2]: K. Itoh,
IEEE Journal of Solid State Circuit
, Vol. 25, No. 3, (1990); pp. 778-789 ([Reference 2] is the original work referenced in [Reference 1]).
[Reference 1] discusses noise arising via word lines when a dynamic random access memory (DRAM) is subjected to amplification. It further discusses, as a case of noise arising via word lines, the phenomenon that a noise voltage on an unselected word line attributable to the coupling capacitance of data lines and the word line gives rise to noise on paired data lines. The impact of that noise is dependent on the structure of the paired data lines (whether an open data line structure or a folded data line structure) and the data line precharging system (whether a VD precharging system or a VD/2 precharging system). As a conclusion, it is stated that the use of a folded data line structure and a VD/2 precharging system helps reduce the noise.
The inventors pertaining to the present application for patent, before filing the application, studied in detail the occurrence of noise attributable to the structure of a 1 Gb DRAM array using micro fabrication technology of 0.16 to 0.13 &mgr;m and the coupling capacitance of data lines and word lines.
FIG. 10
illustrates a planar layout of the DRAM array studied before this application and part of a corresponding circuit diagram. In the planar layout of (a), memory cells (MCs) are disposed at prescribed intersections of data lines (DLs) and word line (WLs). This data line structure is a so-called folded data line structure. Here are shown only the DLs for reading signals out of memory cells, the WLs serving as gates for selecting transistors, regions of diffused layer (ACTs), data line contacts (DLCTs) for connecting ACTs and DLs and storage node contacts (SNCTs) for connecting ACTs and storage nodes of capacitors, but the storage nodes connected to the SNCTs are not shown. Above and underneath the memory array are arranged an upper subword driver array (SWDA-U) and a lower subword driver array (SWDA-D), and two word lines WLs are alternately connected to the upper and lower subword driver arrays. Subword driver will be abbreviated to SWD below as required. To the left and right of the memory array are disposed a left sense amplifier array (SAA-L) and a right sense amplifier array (SAA-R), respectively, and two data lines DLs are alternately connected to the left and right sense amplifier arrays. Sense amplifier will be abbreviated to SA below as required.
These alternate arrangements of SWDs and SAs are intended to ease the tightness of their layout pitches. To look at the boundary between the SWDA-U and the memory array, for instance, there is seen a reiterated pattern of two WLs each passing the boundary and entering the SWD (WL
0
, WL
1
, WL
4
and WL
5
) and ones ending at the boundary (WL
2
, WL
3
, WL
6
and WL
7
). Connection of WLs to the SWD in this manner makes possible easing of the layout pitch per SWD in the direction of data lines to an equivalent of two WLs. For the layout of the SAs as well, the alternate arrangement serves to ease the pitch in the direction of word lines to two pairs of DLs (four DLs). Since memory cells are extremely small in a DRAM, the pitches of WLs and DLs are very fine. This means increased difficulty in laying out SWDs and SAs at prescribed pitches, and accordingly the alternate arrangement can make an important contribution.
Now to look at the relationships of connection between the WLs and the SWD arrays, more specifically to two mutually adjoining memory cells MC
0
and MC
1
which are connected to the DL
0
T, both the WL
0
and the WL
1
connected to these cells are connected to the SWDA-U. On the other hand, to look at two other mutually adjoining memory cells MC
2
and MC
3
connected to the DLOB, they also share the same DLCT, and both the WL
2
and the WL
3
connected to these cells are connected to the SWDA-D. Therefore, in the layout of the memory array of
FIG. 10
, the WLs connected to the two memory cells sharing the DLCT are connected to the same SWD array. In an overall view of the memory array, as the pattern shown in FIG.
10
(
a
) is reiterated vertically and horizontally, all the WLs connected to the MCs connected to the DL
0
T (WL
0
, WL
1
WL
4
and WL
5
in the diagram) are connected to the SWDA-U, and all the WLs connected to the MCs connected to the DL
0
B (WL
2
, WL
3
, WL
6
and WL
7
in the diagram) are connected to the SWDA-D. Accordingly all the word lines connected to memory cells connected to any one data line are connected to the same subword driver array.
These relationships are represented in a circuit diagram which is presented as FIG.
10
(
b
). In a folded data line structure, memory cells are connected to half of the intersections between data lines and word lines. For instance, while the memory cell MC
0
is connected between the DL
0
T and the WL
0
, no MC is connected between the DL
0
B and the WL
0
. An MC consists of a selecting transistor TG and a cell capacitor CS. One of the electrodes of the CS is a plate PL, which is connected in common with other memory cells in the array. The other electrode of the CS is connected to either one of the source or the drain of the TG, and the other of the drain or the source of the TG is connected to the DL. The DL
0
T and the DL
0
B are paired and connected to the SA
0
in the SAA-L, and the DL
1
T and the DL
1
B are connected to the SA
1
in the SAA-R. These SAs amplify a very small voltage difference generated between paired DLs by a signal from the memory cell to a higher level for one DL and to a lower level for the other DL.
Only the parts of MC
0
, MC
1
, MC
2
and MC
3
FIG. 10
are enlarged, with their enlarged layout is shown in FIG.
11
(
a
) and their circuit diagram in FIG.
11
(
b
). Parasitic capacitors emerging between the WLs and DLs of these MCs are also shown. Between the WL
0
or WL
1
and the DL
0
T arises a parasitic capacitance C
00
or C
01
, respectively. Between the WL
0
or WL
1
and the DL
0
B arises a parasitic capacitance C
00
B or C
01
B, respectively. Between the WL
2
or WL
3
and the DL
0
B arises a parasitic capacitance C
02
or C
03
, respectively. Between the WL
2
or WL
3
and the DL
0
T arises a parasitic capacitance C
02
B or C
03
B, respectively.
Cross sections A-A′, B-B′ and C-C′ of the parts pointed by arrows in the layout of FIG.
11
(
a
) are respectively illustrated in FIGS
12
(
a
), (
b
) and (
c
). The cross sections in
FIG. 12
refer to areas near the two word lines WL
0
and WL
1
in the direction represented by arrows in FIG.
11
(
a
). The ACT region on the substrate is the active region of the MOS transistor, while other parts on the substrate are device isolation regions. Over them are wired WLs and DLs, and the DLs are connected to ACTs by oval DLCTs. SNs are storage nodes of cell capacitors CSs, and connected to the ACTs by SNCTs. The upper electrodes PLs of the CSs are commonly connected by cells in the array, and over them are arranged two-layered metallic wires M
2
and M
3
.
To compare C
00
and C
00
B here, as shown in the cross section A-A′ of
FIG. 12
(
a
), the DLCT
0
connected to the DL
0
T passes between the WL
0
and the WL
1
very close to them. The distance between the DLCT
0
and the WL
0
, where the memory cell is made by micro fabrication, is about 30 nm. Therefore, the C
00
, which is a capacitance between the DL
0
T and the WL
0
, is substantially determined by the part between the DL
0
T and the WL
0
.
On the other hand, as shown in the cross section B-B′ of FIG.
12
(
b
), the DL
0

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