Internal clock generating circuit of semiconductor memory...

Details Internal clock generating circuit of semiconductor memory... Internal clock generating circuit of semiconductor memory...

2002-02-07

2003-09-30

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06628155

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to an internal clock generating circuit and method for generating an internal clock which is phase synchronized to an input clock at high speed and with minimum delay.
2. Description of Related Art
In electronic systems having semiconductor memories, a central processing unit (CPU) typically functions as a master and the memory device (which is inter-connected to the CPU through a bus) functions as a slave. The master CPU controls data read/write operations and transmits addresses, commands, and timing information including a data sampling clock to the slave memory device.
For instance, when an external clock (that is aligned or centered to data) is transmitted to a slave through a bus, the slave generates an internal clock for sampling the data. The internal clock should be a data-centered clock synchronized to the external clock. Therefore, if an external clock is a data-aligned clock, the external clock needs to be delayed by an amount of time to generate a data-centered internal clock.
Therefore, a slave should sample an external data with an internal clock having a valid data window. However, as data rate/pin increases, the window for validly clocking data narrows. And, when a data path is slightly different from a clock path in a system, a skew between an external clock and the internal clock or data will be larger. A system using double data rate (DDR), which receives two pieces of data every clock cycle, has an even larger skew than a system having a single data rate (SDR).
Therefore, a slave requires a circuit for controlling a phase of an external clock according to a control signal and for generating an internal clock synchronized to the external clock to meet setup/hold requirements.
When an external clock is controlled by a data sampling internal clock generated through a simple delay line in an internal clock generating circuit, an extra time delay corresponding to an increase/decrease of a unit cycle is generated, thereby limiting performance of the circuit. An internal clock generating circuit generally includes a delay locked loop (DLL) to offset such limitation. One exemplary DLL is described in Japanese patent application laid open No. 11-316618, Nov. 16, 1999. In this reference, multiple DLLs are proposed, each DDL having a different layer structure from the other. The plurality of DDLs are combined to control the phase of external clocks and generate an internal clock having a predetermined amount of time delay.
Typically, because total time delay of a DLL corresponds to a half cycle, it is difficult to generate an internal clock that is synchronized to an external clock within a short amount of time.
FIGS. 1
a
and
1
c
are diagrams showing the time delay of an internal clock phase-synchronized to an input clock phase at an initial state and in a phase-locked state, generated by a conventional internal clock generating circuit, respectively.
FIGS. 1
b
and
1
d
are diagrams showing a phase detector for detecting the time delay of
FIGS. 1
a
and
1
c
, respectively.
In
FIG. 1
a
, a clock (
1
A) is an input clock (e.g., an external clock), and a clock (
1
B) is an internal clock, in which the input clock passes a variable delay line of a DLL in an internal clock generating circuit to generate the internal clock. When the two clocks are applied to a phase detector D
1
having a D-flip flop of
FIG. 1
b
during an initial state of the circuit, the phase detector D
1
latches the two clocks and outputs a low logic value “0” to an output line (OUT
1
) through an output terminal (Q). The logic value “0” is a signal for increasing a time delay of the variable delay line such that a phase of the clock (
1
B) is gradually shifted to the rear of a time axis. In other words, the phase delay between the clocks (
1
A and
1
B) increases during the logic value “0”. When the phase of the clock (
1
B) becomes the phase of a clock (ID) shown in
FIG. 1
c
, i.e., the phase of the clock (
1
B) is delayed by a half cycle (T/2) of an input cycle after a continuous increase in the phase delay of the clock (
1
B), the phase detector D
1
outputs a high logic value “1” to an output line (OUT
1
) through an output terminal (Q) as shown in
FIG. 1
d
. The logic value “1” is a signal for reducing the time delay of the variable delay line.
Therefore, if the time delay of the internal clock (
1
B) is less than the half cycle (T/2) of the input clock, a logic value “0” is output to the output line (OUT
1
). A logic value “1” is output to the output line (OUT
1
) after the time delay of the clock (
1
B) corresponds to the half cycle (T/2). When a DLL is locked (i.e., a normal state), as shown in
FIG. 1
c
, the phase detector (D
1
) alternatively outputs a logic value “1” instead of a logic value “0”.
As described above, a DLL attempts performing a phase locking operation to synchronize the internal clock at T/2 delay from the external clock (as shown in
FIG. 1
c
). That is, the total time delay of the DLL having a variable delay line is T/2 instead of T. Thus, additional delay line is required to further delay the external clock to generate an internal clock phase-synchronized to an external clock.
Furthermore, because an internal clock phase-synchronized to an external clock is generated through a conventional DLL circuit requiring additional delay line, the time for generating the internal clock becomes longer. As a result, conventional internal clock generating circuits to achieve synchronization require additional delay and a longer time.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the aforementioned problem and provide an internal clock generating circuit and method for generating an internal clock synchronized to an external clock.
It is another object of the present invention to provide a circuit and method for generating an internal clock for accurately sampling data even if there is a skew between a clock and input data in a semiconductor memory device.
It is still another object of the present invention to provide an internal clock generating circuit and method for generating an internal clock synchronized to an external clock with a minimized delay stage.
It is further object of the present invention to provide an internal clock generating circuit and method for controlling the time delay of an internal clock by about one cycle of an input clock.
It is a still further object of the present invention to provide a circuit and method for simplifying the time delay line for delaying an input clock and for generating an internal clock synchronized to the input clock and a shifted clock of the input clock within a short period.
According to one aspect of the present invention, there is provided an internal clock generating circuit comprising a first delay control circuit for generating the first clock having a time delay of up to T/2 (where T is a cycle of an input clock) from the input clock and for generating a first variable delay control signal; and a second delay control circuit for generating a second clock in response to the first variable delay control signal, the second clock having the time delay of greater than T/2 from the input clock at an initial state and having the time delay of about T from the input clock in a phase-locked state.
In a preferred embodiment, the first delay control circuit comprises a first variable delay line for delaying a phase of the input clock to generate the first clock in response to the first variable delay control signal; a first phase comparison unit for comparing the first clock with the input clock to generate a first up/down counting control signal; and a first counter for counting the input clock to generate the first variable delay control signal in response to the first up/down counting control signal. The first variable delay line delays the phase of the input clock until the first clock has the time delay of up to T/2 from the input clock.
In a preferred embod

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