Amplifiers – With periodic switching input-output
Reexamination Certificate
2001-09-28
2003-09-09
Choe, Henry (Department: 2817)
Amplifiers
With periodic switching input-output
C327S124000
Reexamination Certificate
active
06617918
ABSTRACT:
BACKGROUND
This invention is generally related to input/output (i.e., I/O) circuits and in particular to multi-level receiver circuits with digital outputs.
I/O circuits act as the interface between different logic functional units of an electrical system. The functional units may be implemented in separate integrated circuit dies (i.e., IC chips) of the system. These chips may be in separate IC packages that have been soldered to a printed wiring board (i.e., PWB). The chips communicate with each other over one or more conductive transmission lines. The transmission lines may be a parallel bus formed on a PWB, and they may be of the point-to-point or multi-drop variety. Alternatively, the transmission line may be a serial link such as a coaxial cable. In both cases, each chip has an I/O circuit that includes a driver and a receiver for transmitting and detecting symbols. The driver and receiver translate between on-chip signaling and signaling that is suitable for high speed transmission (e.g., at several hundred megabits per second and higher) over a transmission line. In a ‘bidirectional link’, the driver and receiver pair are connected to the same transmission line.
In multi-level data communications, each transmitted symbol can have one of three or more values. For example, each symbol in a four pulse amplitude modulation (i.e., 4 PAM) link may only be a 0, 1, 2, or 3. In contrast, each symbol in a binary communication link may only be 0 or 1. For the binary link, the two symbol values may be detected using a single comparator whose reference level is fixed at the midpoint between the 0 and 1 nominal signal levels. A single digital ‘bit’ at the output of the comparator yields the symbol value. In contrast, a 4 PAM multi-level receiver may use three comparators whose respective reference levels have been fixed with respect to the four nominal signal levels, such that four different signal levels can be discerned. A three-bit number that appears at the output of the comparators identifies any one of four detected symbol values. Since two bits can be used to represent four different values, an encoder may be added in the receiver to encode the three bit number into two bits, such that each symbol is detected as a two-bit number. This concept can be readily extended to communication links in which each symbol represents greater than two bits.
REFERENCES:
patent: 4754169 (1988-06-01), Morris
patent: 4987327 (1991-01-01), Fernandez et al.
patent: 5563598 (1996-10-01), Hickling
patent: 5796301 (1998-08-01), Tanabe et al.
patent: 5940235 (1999-08-01), Sasaki et al.
patent: 6194965 (2001-02-01), Kruczkowski et al.
patent: 6252454 (2001-06-01), Thompson et al.
patent: 6348882 (2002-02-01), Ciccone et al.
patent: 6388521 (2002-05-01), Henry
Blakely , Sokoloff, Taylor & Zafman LLP
Choe Henry
Intel Corporation
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