Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-11-30
2003-08-12
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C363S059000
Reexamination Certificate
active
06605983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage conversion circuit used, for example, in the power supply of a liquid crystal panel and configured to output two voltages, that is, a positive and negative voltage, based on an input dc voltage.
2. Description of the Related Art
A first example of a voltage conversion circuit of this type according to the prior art (referred to below as first prior art circuit) is shown in FIG.
29
.
As shown in
FIG. 29
this first prior art circuit has a timing signal generator
1
, MOS transistors Q
1
to Q
6
that are controllably switched ON/OFF by the output from the timing signal generator
1
, capacitors C
1
and C
2
producing a positive voltage twice the dc input voltage Vin according to the ON/OFF operation of MOS transistors Q
1
to Q
4
, capacitors C
3
and C
4
producing a negative voltage −1 times the dc input voltage Vin according to the ON/OFF operation of MOS transistors Q
1
, Q
2
, Q
5
, and Q
6
, and a level shift circuit
2
.
MOS transistors Q
1
and Q
5
of MOS transistors Q
1
to Q
6
are n-type, and MOS transistors Q
2
to Q
4
and Q
6
are p-type. As shown in the figure, level shift circuit
2
consists of resistors, diodes, and the like.
Note also that the timing signal generator
1
and MOS transistors Q
1
to Q
4
enclosed in the dotted square in
FIG. 29
in this first prior art circuit, are integrated onto a single semiconductor substrate forming an IC chip. The level shift circuit
2
, MOS transistors Q
5
and Q
6
, and capacitors C
1
to C
4
are separate components externally connected to the IC chip.
The operation of this first prior art circuit is described next with reference to
FIG. 29
to FIG.
31
.
The timing signal generator
1
generates and supplies timing signals (control signals) A, XB, XA
2
, XB
2
to the gate of MOS transistors Q
1
to Q
4
, respectively, to switch the MOS transistors Q
1
to Q
4
ON or OFF. Timing signals A and XB from timing signal generator
1
are level shifted by the level shift circuit
2
, which outputs the resulting signals AS and XBS to the gates of MOS transistors Q
5
and Q
6
to switch MOS transistors Q
5
and Q
6
ON or OFF.
This operation causes MOS transistors Q
1
, Q
3
, Q
5
to be ON and MOS transistors Q
2
, Q
4
, Q
6
to be off in period T
1
shown in FIG.
30
. The circuit equivalent to operation period T
1
is shown in FIG.
31
A. Capacitor C
1
is charged by the dc source Vin. The positive output voltage VOUT
1
is the sum of the source voltage Vin and the stored charge voltage of capacitor C
2
. At the same time the charge of capacitor C
3
is shared with capacitor C
4
, and the end voltage of capacitor C
3
becomes the negative output voltage VOUT
2
.
In period T
2
in
FIG. 30
MOS transistors Q
2
, Q
4
, Q
6
switch on, and MOS transistors Q
1
, Q
3
, Q
5
switch off. The circuit equivalent to period T
2
is shown in FIG.
31
B. Capacitor C
3
is charged by the dc source Vin, and the negative output voltage VOUT
2
is the voltage across capacitor C
4
. At the same time, the charge of capacitor C
1
is shared with capacitor C
2
, and the positive output voltage VOUT
1
becomes the sum of the source voltage Vin and the stored charge voltage of capacitor C
1
. The voltage drops VF are due to the forward voltage drops of the diodes within the level shift circuit
2
. This first prior art circuit thus operates as a charge-pump type dc—dc converter by simply repeating the operation of periods T
1
and T
2
.
As a result of this operation, the values of positive output voltage VOUT
1
and negative output voltage VOUT
2
from this first prior art circuit can be determined from equations (1) and (2) where the ground GND potential is 0 V.
VOUT
1
=
Vin
·2 (1)
VOUT
2
=Vin
·(−1) (2)
where Vin is the dc input voltage.
FIG. 32
shows the configuration of the MOS transistors Q
1
to Q
4
inside the dotted line in
FIG. 29
integrated to a semiconductor substrate in this first prior art circuit.
As shown in
FIG. 32
, reference numeral
11
is a p-type semiconductor substrate. An NMOS transistor Q
1
with a source S, gate G, and drain D is formed in this p-type semiconductor substrate
12
. Three n-wells
11
to
14
are also formed in p-type semiconductor substrate
11
, and PMOS transistors Q
2
to Q
4
each having a source S, gate G, and drain D are formed in each of these n-wells
12
to
14
.
Connections between parts of MOS transistors Q
1
to Q
4
and the p-type semiconductor substrate
11
are indicated by the bold lines in FIG.
32
.
A second example of a voltage conversion circuit of this type according to the prior art (referred to below as second prior art circuit) is described next with reference to FIG.
33
.
As shown in
FIG. 33
, this second prior art circuit replaces MOS transistors Q
5
and Q
6
of the first prior art circuit with diodes D
1
, D
2
, and eliminates the level shift circuit
2
. The configuration of other parts is identical to the configuration of the first prior art circuit, and further description thereof is thus omitted.
Operation of this second prior art circuit is basically the same as that of the first prior art circuit except that since the switching devices are diodes, and not complementary MOS transistors, a voltage drop, VFa, equivalent to the forward voltage drop of the diodes is introduced at the output. Therefore, VOUT
2
of this embodiment differs from that of the embodiment of
FIG. 29
in that the negative output voltage VOUT
2
is as shown in equation (3).
VOUT
2
=[
Vin
·(−1)]+[
VFa·
2] (3)
where VFa is the forward voltage drop of diodes D
1
, D
2
.
A problem with the first prior art circuit as shown in
FIG. 29
is that it is not possible to reduce the overall size of the circuit because of the many externally connected components, including parts of the level shift circuit
2
and MOS transistors Q
5
and Q
6
.
Furthermore, because a level shift circuit
2
is needed, the level of timing signal A from timing signal generator
1
is gradually lowered by level shift circuit
2
, resulting in signal AS (see
FIG. 30
) being applied to the gate of MOS transistor Q
5
. This drop increases if the frequency of signal AS is low, and potentially adversely affects the operation of MOS transistor Q
5
.
The second prior art circuit has an advantage over the first prior art circuit in that there are fewer external parts. However, the negative output voltage VOUT
2
is decreased by the forward voltage VFa component of the diode as shown by equation (3), and power conversion efficiency thus drops.
OBJECTS OF THE INVENTION
Therefore, with consideration for the above problems, an object of the present invention is to provide a voltage conversion circuit that reduces the number of external parts as much as possible and thus enables an overall reduction in size while maintaining high power conversion efficiency.
SUMMARY OF THE INVENTION
To resolve the above problems, a voltage conversion circuit includes a plurality of MOS transistors that are switched ON/OFF to charge a capacitance with an input dc voltage, and this charging voltage is used to convert the input dc voltage to a specific positive and negative output voltage, wherein: the plural MOS transistors include PMOS and NMOS transistors for positive voltage conversion, and a NMOS transistor for negative voltage conversion; the NMOS transistors for positive voltage conversion are formed in a p-type semiconductor substrate; the PMOS transistors for positive voltage conversion are formed in an n-type first well formed in the p-type semiconductor substrate; and the NMOS transistor for negative voltage conversion is formed in a p-type third well, which is formed in an n-type second well formed in the p-type semiconductor substrate.
The present invention can thus form the MOS transistors used for voltage conversion in the same p-type semiconductor substrate, and can therefore reduce the external components to capacitors only. It is therefore possi
Haro Rosalio
Lam Tuan T.
Nguyen Hiep
Seiko Epson Corporation
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