Phase locked loop circuits, systems, and methods

Details Phase locked loop circuits, systems, and methods Phase locked loop circuits, systems, and methods

1999-03-31

2003-09-09

Mis, David C. (Department: 2817)

Oscillators

Ring oscillators

C331S017000, C331S045000

Reexamination Certificate

active

06617934

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to analog and digital processors and methods, and more particularly to phase locked loop circuits, systems, and methods for charge coupled device (CCD) cameras and CMOS imagers.
1. Field of the Invention
Charge coupled device (CCD) cameras are configured to capture signals according to many different CCD output formats and pixel configurations. A certain class of CCD imagers requires 4-phase pixel timing to read out the horizontal shift register. Each of these four clocks is required to run at a predetermined pixel rate. However, the phase of each such clock with respect to the subsequent clock is shifted by 45 degrees, or ⅛ of a clock period. Currently, to generate such precise relative phases, systems use clock frequencies which are eight times the pixel rate. This results in a system requiring very high clock frequencies (e.g., 120 MHz) to accommodate the indicated phase requirements.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a 1× phase locked loop is used to generate eight clock signals, each phase shifted from the previous one in time by ⅛th of the clock period. These eight clock signals are used to generate horizontal clocking signals on one of eight equal phase steps within a clock period. In particular, the phase locked loop outputs eight clock phases, or four clock phases and their complements, each running at the pixel rate, thereby eliminating the need for higher speed circuitry. According to one embodiment, the phase locked loop employs an oscillator with four stages, three inverting and one non-inverting. The output of each stage is shifted in phase 45 degrees from the previous one, in terms of pixel clock rate. According to one embodiment, differential stages are employed. According to one embodiment of the present invention, all of the four stages are substantially identical structures. To achieve non-inversion, the output of the last stage is connected or swapped into the input of the first stage. This results in the same delay for both inverting and non-inverting stages, permitting the ring oscillator to oscillate with each stage's output remaining at 45 degrees of the previous stage's phase.


REFERENCES:
patent: 5180994 (1993-01-01), Martin et al.
patent: 5298870 (1994-03-01), Cytera et al.
patent: 5936475 (1999-08-01), Tchamov et al.
patent: 5945881 (1999-08-01), Lakshmikumar

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