Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-12-22
2003-09-09
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010
Reexamination Certificate
active
06617842
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a testing technique for a semiconductor device. More particularly, it relates to a method, a device and a system for testing in which a test pattern for inspection is prepared based on trace data in the operating state of the semiconductor device mounted on implemented equipment, and to software therefor.
BACKGROUND OF THE INVENTION
In characterization tests for a semiconductor device, which are conducted in the course of research and development, a series of comprehensive tests are carried out. These include tests such as various operational margin tests with varying power or timing, in addition to DC parametric tests, functional tests or AC parametric tests for semiconductor devices. For example, high-performance automatic testing equipment (ATE) using sampling data prescribing operational specifications for semiconductor devices can be used.
In the manufacturing process for a semiconductor device, a mass production test, also termed a final test, is carried out on a packaged semiconductor device following a wafer test and dicing and bonding steps to guarantee that the semiconductor device meets minimum electrical specifications. Usually, on a device under test (DUT), continuity and leakage tests, basic functional tests, DC parametric tests and, as necessary, minimum margin tests are performed using a low-cost automatic testing device for mass production. The automatic testing equipment is connected to an auto-handler which sorts the devices tested according to classes and grades (or categories) based on test results.
In this final test, shorter test time is of paramount importance, so that test items and test patterns selected as necessary minimum items may be used in testing without performing comprehensive tests.
However, there are occasions in which a semiconductor device product, verified to be good in the final test stage and marketed, suffers from malfunctions when mounted and operated on electronic equipment.
In other words, the final test is usually conducted using low-cost automatic testing equipment. Hence, there is a limit to the pattern length of a test pattern (test vector length) or the number of different patterns for functional tests. For example, a device failure undetectable with a test pattern used in a final test is sometimes detected by haphazard after product shipment.
With recent progress in device miniaturization, leading to high integration and high functionality, the number of gates mounted on a single chip is drastically increased. The increased logical complexities of these chips make it more and more difficult to provide test patterns capable of detecting all of the defects dependent on combinations of input/output patterns of the logical integrated circuits. In the case of a program-controlled logic IC, particularly, the combination of input/output patterns to the logical IC is varied depending on the contents, the operating (running) states, or the haphazard phenomenon. Thus, in reality it is almost impossible to provide all of these combinations for testing logical ICs at the outset.
Several methods are currently employed for generating a test pattern for use in automatic testing equipment that tests semiconductor devices. Among these methods, one method uses a tool for converting the simulated result obtained by a logical simulator used in designing a semiconductor device into a test pattern for conversion to a test pattern for automatic testing equipment in question. Another method uses an automatic pattern generating tool (APG). A third method generates a test pattern and uses a failure simulator taking into account the rate of failure detection. These methods generate test patterns based on simulation.
As another method, a test pattern is acquired by using a real device. As a typical time-honored technique, a previously provided input pattern (random pattern) is applied to a Known Good Device (KGD) to sample an output from the KGD. The sampled output as a pattern of expected values is synthesized with an input pattern to generate a test vector.
There is another device for generating a test pattern that acquires a signal waveform in the course of the operation with the semiconductor integrated device mounted on implemented equipment. As described in JP Patent Kokai JP-A-7-306245, a well-known method involves sampling a terminal waveform of a semiconductor integrated device mounted on implemented equipment, appending the input/output information input by a manufacturer of the implemented equipment as to the terminal waveform, using a waveform editor of testing equipment, and acquiring a test pattern for inspection from the resulting data. In this method, the pattern quality is appreciably influenced by whether the input/output information acquired from the manufacturer of the implemented equipment is the correct information. The above-mentioned JP Patent Kokai JP-A-7-306245 proposes a testing method comprising: pattern generating means made up of a data conversion circuit for acquiring the signal waveform data at the time of operation at the terminal of an LSI under test by a logic analyzer and converting the data into an input pattern for testing, and a data memory for storing an input pattern output by the data conversion circuit; a voltage setting means for setting a variety of voltages, inclusive of a source voltage VDD, a high level input voltage VIH, a low level input voltage VIL, and a grounding voltage, for providing a difference in input and output current values produced by the driving input of a preset input pattern and supplying the so-set voltages to the LSI; and an input/output information holding means for receiving an input pattern output by pattern generating means for applying the input pattern received to a specified terminal designated for current measurement to measure the input and output currents produced in the specified terminal designated for current measurement to measure the input and output currents produced in the specified terminal, detecting the difference between the input and output currents, verifying PASS/FAIL in the input pattern and extracting and holding the FAIL information. The input pattern for testing, generated by the pattern generating means, is synthesized with the FAIL information output by the input/output information holding means, to generate a test pattern for inspection corresponding to the LSI. The entire disclosure of JP-A-7-306245 is herein incorporated by reference.
SUMMARY OF THE DISCLOSURE
However, various problems have been encountered during investigations toward the present invention. Namely, in the current state of the art, there is provided no tool for reflecting the malfunction information pertinent to the semiconductor device products when a test pattern of testing equipment is used during a run on implemented equipment.
If malfunction or failures (flaws) occur on the implemented equipment, and the semiconductor device product is responsible for the failure, the semiconductor device product is exchanged with a KGD, by way of a repair service to check whether or not the implemented equipment operates normally. If, as a result of such exchange, the implemented equipment operates normally, the result is acceptable to a user. However, there are occasions on which the malfunction is not resolved even by exchange with a KGD. For example, if the semiconductor device is a program-controlled CPU or a peripheral device, memory device etc., adapted for exchanging data with a program-controlled CPU, the input/output pattern or the timing might change, thereby producing a malfunction as a result of the failure of a device with respect to a certain combination of randomly occurring pattern sequences due to changes in the input/output pattern or timing depending on the operating states or programs executed on the CPU.
Even if, in such a case, the semiconductor device is exchanged for a KGD and mounted on the implemented equipment, the KGD may undergo malfunction for such a specific pattern combination.
If the malfunction of the semicon
Nishikawa Katsumi
Shibata Kazuo
Hayes & Soloway P.C.
Kobert Russell M.
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