Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-04-09
2003-04-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S102000, C365S149000
Reexamination Certificate
active
06549445
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a semiconductor memory device having a memory cell array structure that can deal with many input/output data simultaneously, and a method of fabricating such a semiconductor memory device.
2. Description of the Background Art
In accordance with the recent development of information communication technology, the need arises for a semiconductor memory device that can handle many data at high speed and in parallel in addition to the large memory capacity. A typical example is the application of carrying out data processing with respect to image data.
To accommodate the need, a semiconductor memory device is employed having a structure including a plurality of banks capable of read and write operations independently to process a large amount of data simultaneously by a plurality of global data lines arranged in parallel.
In a semiconductor memory device having a memory cell array of high complexity, the redundancy repair technology of repairing the defective portion of the regular memory cell generated during fabrication by a spare memory cell provided in advance on the same chip becomes an important element in ensuring the product yield.
In accordance with the increase of the memory capacity, Japanese Patent Laying-Open No. 8-77793, for example, discloses the art to carry out layout designing efficiently by repairing a redundancy circuit among a plurality of memory cell arrays (corresponding to banks) capable of reading and writing data independently, as the technique to carry out redundancy reparation efficiently.
In such a semiconductor memory device having many global data lines arranged, increase of the parasitic capacitance in the global data lines arranged in multiple arrangement becomes a problem. This is because the arrangement pitch of the global data lines is reduced by providing so many global data lines in parallel. In a semiconductor memory device of such a structure, the global data line arrangement becomes a critical factor in increasing the speed of data input/output and reducing power consumption.
Since the circuit used for redundancy repair generally requires a large layout area, the appropriate provision of the circuit for redundancy repair is significant in reducing the layout area in such a memory array that has many global data lines arranged in parallel.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a structure that can have parasitic capacitance of global data lines reduced in a semiconductor memory device including numerous global data lines, capable of a large amount of data input/output in parallel, and a fabrication method thereof.
According to an aspect of the present invention, a semiconductor memory device includes a memory cell array, a plurality of read data lines, a plurality of write data lines, a plurality of read column select lines, a plurality of write column select lines, a read select gate, and a write select gate.
The memory cell array includes a plurality of memory cell blocks arranged in a matrix. Each memory cell block includes a plurality of memory cells arranged in a matrix. The plurality of read data lines are shared between a plurality of memory cell blocks adjacent in the column direction. Each read data line is arranged for every L (L is a natural number) memory cell columns to transmit data read out from the memory cell array. The plurality of write data lines are shared between a plurality of memory cell blocks adjacent in the column direction. Each write data line is arranged for every M (M is a natural number) memory cell columns to transmit data to be written into the memory cell array. The plurality of read column select lines transmit a read column select signal to select one memory cell column from the L memory cell columns in each memory cell block. The plurality of write column select lines transmit a write column select line to select one memory cell column from M memory cell columns in each memory cell block. The read select gate is provided for every L memory cell columns in each memory cell block to transmit the data read out from the selected memory cell column in response to the read column select signal to a corresponding one of the plurality of read data lines. The write select gate is provided for every M memory cell columns in each memory cell block to transmit the write data from one of the plurality of write data lines to the selected memory cell column in response to a write column select signal.
According to another aspect of the present invention, a semiconductor memory device formed on a semiconductor substrate includes a memory cell array region, a transistor layer, a capacitor layer, a first interconnection layer, a second interconnection layer, and a plurality of global data lines.
The memory cell array region includes a plurality of memory cells arranged in a matrix. Each memory cell includes an access transistor and a data storage capacitor. The transistor layer is formed on the semiconductor substrate. A transistor including an access transistor is arranged at the transistor layer. The capacitor layer is formed at the top surface of the transistor layer up to a first height in the memory cell array region. A data storage capacitor is arranged at the capacitor layer. The first interconnection layer is formed at the top surface of the transistor layer at a height between a second height that is lower than the first height and a third height higher than the first height, outside the memory cell array region. The second interconnection layer is arranged in common at the memory cell array region and outside the memory cell array region at the top surface of the transistor layer at a height between a fourth height higher than the third height and a fifth height higher than the fourth height. The plurality of global data lines are arranged at the second interconnection layer to transmit data read and written with respect to the plurality of memory cell arrays.
According to a further aspect of the present invention, a fabrication method of a semiconductor memory device includes the steps of forming a transistor layer on a semiconductor substrate, forming a capacitor layer on a memory cell array region, forming an interlayer insulation film on the capacitor layer, providing a region where a reference line is to be arranged to couple a cell plate layer formed at the top surface side of the capacitor layer to the reference potential by grinding the cell plate layer partially, forming a metal film after a portion of the cell plate layer is ground, working on the metal film according to a predetermined wiring pattern to form a plurality of lines including the reference line.
The main advantage of the present invention is that parasitic capacitance is suppressed by alleviating the wiring pitch in the horizontal direction for either the plurality of read data lines or the plurality of write data lines without significantly increasing the number of the plurality of read column select lines and the plurality of write column select lines. As a result, the speed can be increased and power consumption reduced in either the data read operation or the data write operation.
The parasitic capacitance of the wiring formed at the second interconnection layer where a plurality of global data lines are arranged can be suppressed than the case where the interconnection layer formed at the memory cell region and outside the memory cell region is designed in common. Therefore, the speed can be increased and power consumption reduced in the data read and write operations carried out by the plurality of global data lines.
The reference line to fix the potential of the cell plate can be arranged without having to provide a contact hole to the cell plate. Since the aspect ratio of the contact hole formed on the semiconductor substrate does not have to be changed greatly, fabrication of the contact hole in the ent
Ooishi Tsukasa
Tanizaki Hiroaki
Le Thong
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
LandOfFree
Semiconductor memory device including plurality of global... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device including plurality of global..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device including plurality of global... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3073952