Method of forming a recessed magnetic storage element

Details Method of forming a recessed magnetic storage element Method of forming a recessed magnetic storage element

2001-06-11

2003-04-22

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S003000

Reexamination Certificate

active

06551852

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to MRAM semiconductor structures and, in particular, to a method of forming recessed MRAM cells.
BACKGROUND OF THE INVENTION
Magnetic random access memories (MRAMs) employ magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, which in turn depend on the alternative states of magnetization of thin magnetic multilayer films forming each memory cell. As such, the MRAM cell has two stable magnetic configurations, a high resistance state representing a logic state 0 (or 1) and a low resistance state representing a logic state 1 (or 0).
A typical multilayer-film MRAM includes a number of bit or digit lines intersected by a number of word lines. At each intersection, at least one film of a magnetically coercive material is interposed between the corresponding bit line and digit line. Thus, this magnetic material and the films from the bit and digit lines form a magnetic memory cell which stores a bit of information.
The basic memory element of an MRAM is a patterned structure of a multilayer material, which is typically composed of a stack of different materials, such as copper (Cu), tantalum (Ta), permalloy (NiFe) or aluminum oxide (Al
2
O
3
), among others. The stack may contain as many as fourteen different overlapping material layers. Fabrication of such stacks requires deposition of the thin magnetic materials layer by layer, according to a predefined order.
FIG. 1
illustrates an exemplary MRAM structure including MRAM stacks
22
which have three respective associated bit or digit lines
18
. The digit lines
18
, typically formed of copper (Cu), are first formed in an insulating layer
16
formed over an underlayer
14
containing fabricated integrated circuits formed over substrate
10
. Underlayer
14
may include, for example, portions of integrated circuitry, such as CMOS circuitry. First magnetic layers (pinned layers)
20
, typically formed of a ferromagnetic materials, are provided over the digit lines
18
. A pinned layer is called “pinned” because its magnetization direction requires a very high magnetic field to switch magnetization direction. Second magnetic layers (sense layers)
21
are free to switch magnetization direction with a much lower magnetic field. This way, information is stored in the magnetic layers of the memory cell as directions of the magnetization vectors which affect the resistance of the cell.
High density patterning, alignment and small cell size are very difficult to form in arrays of submicron MRAM devices. Improved fabrication techniques to form smaller and denser magnetic memory cells are desirable as they would allow the number of memory cells supported by a single CMOS supporting circuit to be greatly increased. It is also desirable to reduce the cost and complexity of fabricating magnetic memory cells and to reduce the number of patterning steps required in the fabrication of the memory cell while reducing fabrication errors.
SUMMARY OF THE INVENTION
The present invention provides a method for forming reduced area MRAM structures, such as pinned layers and underlying digit lines and sense layers, formed over various underlayers of an integrated circuit structure. According to the present invention, recessed MRAM structures, such as recessed pinned and sense magnetic layers of an MRAM stack, are formed over recessed digit lines, such as recessed copper lines, formed in an insulating layer.
These and other features and advantages of the invention will be more apparent from the following detailed description which is provided in connection with the accompanying drawings, which illustrate exemplary embodiments of the invention.


REFERENCES:
patent: 5841692 (1998-11-01), Gallagher et al.
patent: 6153443 (2000-11-01), Durlam et al.
patent: 2002/0096775 (2002-07-01), Ning

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