Television – Synchronization – Locking of video or audio to reference timebase
Reexamination Certificate
2000-06-23
2003-03-25
Lee, Michael H. (Department: 2614)
Television
Synchronization
Locking of video or audio to reference timebase
C348S571000, C348S718000
Reexamination Certificate
active
06538700
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a synchronizing conversion method and apparatus as well as a recording medium, and more particularly to a synchronizing conversion apparatus and method as well as a recording medium suitable for use to convert a synchronizing frequency, for example, of an image signal into a different frequency.
In order to output an image signal in synchronism with a frequency (hereinafter referred to as output synchronizing signal) different from a synchronizing frequency (hereinafter referred to as an input synchronizing signal) of a frame synchronizing signal of the image signal, usually a method is used wherein the image signal is written into a frame memory in synchronism with the input synchronizing signal and then read out from the frame memory in synchronism with the output synchronizing signal. However, from a difference in cycle length between the input synchronizing signal and the output synchronizing signal, it sometimes occurs that the write address for the frame memory outpaces the read address or conversely the read address outpaces the write address.
The phenomenon is described in more detail. Referring to
FIG. 1A
, the axis of abscissa indicates the time and the axis of ordinate indicates the address of a frame memory, and writing and reading out timings of an image signal into and from the frame memory are illustrated. When the cycle of the output synchronizing signal is shorter than the cycle of the input synchronizing signal, the read address outpaces the write address at a rear half portion of the read cycle (R
2
) for the second frame. Consequently, the image signal of the first frame is read out as the image signal of the second frame at and later than the rear half portion of the read cycle of the second frame. Further, in the read cycle (R
3
) for the third frame, since the read address precedes the write address completely, the image signal of the second frame is read out as the image signal of the third frame.
Referring to
FIG. 1B
, the input synchronizing signal WV
n
, and the output synchronizing signal RV
n
(n=0, 1, 2, . . . ) indicate timings at which the 0th frame of the image signal is written and read out, respectively. A state wherein one cycle of the output synchronizing signal is included within one cycle of the input synchronizing signal like, for example, a state wherein one cycle from an output synchronizing signal RV
2
to a next output synchronizing signal RV
3
is included within one cycle from an input synchronizing signal WV
2
to a next input synchronizing signal WV
3
, indicates that the read address has outpaced the write address.
On the contrary, when the cycle of the output synchronizing signal is longer than the cycle of the input synchronizing signal, the write address outpaces the read address at a rear half portion of the read cycle (R
2
) for the second frame as seen in FIG.
2
A. Consequently, the image signal of the third frame is read out as the image signal of the second frame at and later than the rear half portion of the read cycle of the second frame. Further, in the read cycle (R
3
) for the third frame, since the write address precedes the read address completely, the image signal of the fourth frame is read out as the image signal of the third frame.
Referring to
FIG. 2B
, a state wherein one cycle of the input synchronizing signal is included within one cycle of the output synchronizing signal like, for example, a state wherein one cycle from an input synchronizing signal WV
3
to a next input synchronizing signal WV
4
is included within one cycle from an output synchronizing signal RV
2
to a next output synchronizing signal RV
3
, indicates that the write address has outpaced the read address.
A method for solving the problem of such outpacing between a write address and a read address is disclosed, for example, in Japanese Patent Laid-Open No. Hei 9-18740 wherein a phase difference between the input synchronizing signal and the output synchronizing signal is detected and the write address for the frame memory is controlled based on the phase difference thus detected.
The method of controlling the write address in this manner, however, has a subject to be solved in that, in order to convert a synchronizing frequency of an image signal into a plurality of signals of different output synchronizing frequencies, a number of circuits each including a frame memory, a write control circuit and so forth equal to the number of kinds of output synchronizing signals to be converted must be provided.
The method described above has another subject to be solved in that, since it can be applied only where the frequencies of the input synchronizing signal and the output synchronizing signal are invariable (stable), for example, if the input synchronizing signal or the output synchronizing signal suffers from fluctuation in frequency, then outpacing compensation cannot be executed accurately.
The method described above has a further subject to be solved in that, since outpacing compensation is executed at any time, repetition of an image or jumping of an image originating from the outpacing compensation may possibly occur in a series of scenes which exhibit some continuous motion, resulting in a visually unnatural image.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronizing conversion apparatus and method as well as a recording medium wherein outpacing compensation can be executed with a circuit construction including a comparatively small number of components.
In order to attain the object described above, according to the present invention, a read address of a frame memory is controlled appropriately.
In particular, according to an aspect of the present invention, there is provided a synchronizing conversion apparatus for converting a synchronizing frequency of an image signal, comprising an image memory, write means for writing the image signal into the image memory in synchronism with a first synchronizing frequency signal inputted thereto, read means for reading out the image signal from the image memory in synchronism with a second synchronizing frequency signal inputted to the read means and having a frequency different from that of the first synchronizing frequency signal, detection means for detecting a phase difference between the first and second synchronizing frequency signals, prediction means for predicting occurrence of outpacing between a read address and a write address for the image memory based on the phase difference detected by the detection means, modification means for modifying a reading out timing of the read means in response to a result of the prediction of the prediction means, and delay compensation means for executing delay compensation for the image signal read out by the read means in response to the result of the prediction of the prediction means.
The detection means may additionally detect a variation of the phase difference which arises from a fluctuation of the frequency of the first or second synchronizing frequency signal.
The synchronizing conversion apparatus may further comprise scene change detection means for detecting a scene change of the image signal, and the modification means may modify the reading out timing of the read means in response to a timing at which a scene change of the image signal is detected by the scene change detection means.
The synchronizing conversion apparatus may comprise two or more read systems each of which includes the read means, detection means, prediction means, modification means and delay compensation means.
In this instance, the synchronizing conversion apparatus may further comprise arbitration means for arbitrating the writing process of the write means into the image memory and reading out processes of the read means of the read systems from the image memory. The prediction means may predict occurrence of outpacing between the read address and the write address for the image memory based on the phase difference detected by the detection means and a time req
Fukuda Kyoko
Kobayashi Hiroshi
Ohta Masashi
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