Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2001-10-04

2003-03-25

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C257S780000, C257S784000

Reexamination Certificate

active

06538326

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device used in a semiconductor integrated circuit and a manufacturing method thereof, and more particularly concerns a semiconductor device which is provided with a bonding pad formed above an active region on a surface of a semiconductor substrate and a manufacturing method thereof.
BACKGROUND OF THE INVENTION
There is a tendency in a semiconductor integrated circuit that its integration level (the number of semiconductor elements integrated on a chip) has been increased and its chip size has become larger, in accordance with the progress in manufacturing an electronic device with higher functions and performance which is equipped with semiconductor integrated circuits. On the other hand, in response to the need for a smaller package containing a semiconductor integrated circuit, a chip has been downsized by reducing the processing size (reducing the design rule) and by miniaturizing the package containing the semiconductor integrated circuit.
A semiconductor integrated circuit chip can be roughly divided into two regions: one is an operation region (also referred to as an active region in some cases) inside the chip, and the other is a bonding pad region formed on a surface of the chip. The operation region includes a region on which semiconductor elements such as a transistor, etc. are provided (an active region), and a region of metal wiring connecting the semiconductor elements (a wiring region). The bonding pad region is a region on which bonding pads are formed. A bonding pad is an electrode for electrical connection to an external section by, for example, wire bonding using a fine gold wire, for the input/output of a signal to/from the semiconductor integrated circuit and for other purposes. Generally, the bonding pads are provided on the perimeter of a chip, avoiding a region overlying the active region of a semiconductor substrate. This is to prevent stress caused at the bonding pad when carrying out bonding such as wire bonding due to mechanical pressure, etc. applied to the bonding pad, from being applied to the action region constituting the semiconductor element. In general, the bonding pad is a rectangle in which the length of one side is about 50 &mgr;m to 100 &mgr;m, and a plurality of the bonding pads are placed on the perimeter of the chip at intervals about 10 &mgr;m to 20 &mgr;m.
Formerly, it was enough to provide one layer of metal wiring for connecting semiconductor elements on a semiconductor integrated circuit chip. However, in accordance with the development in functions and performance and the increase in the integration level, the wiring has become longer and complicated, causing defects such that a signal cannot be transmitted correctly. To solve such a problem, a multilayer wiring structure, in which a plurality of wiring layers are laminated via inter-layer insulation films, has been proposed. This structure increase flexibility and facilitates the improvement in the function and performance of semiconductor integrated circuits, and the improvement of their integration level.
Meanwhile, as semiconductor integrated circuits come to have higher functions and performance, the number of terminals used for input/output, etc. increases accordingly, reaching several hundreds to nearly one thousand. Since one bonding pad is required for one terminal, the number of bonding pads required also increases in response to the increase in the number of terminals, and several hundreds to nearly one thousand bonding pads are required. Along with such an increase in the number of bonding pads, the area of the bonding region on a chip surface is increasing. Therefore, chip size reduction in a semiconductor integrated circuit (miniaturization of a semiconductor integrated circuit) cannot be achieved, failing to satisfy the need for the miniaturization of an electronic device equipped with a semiconductor integrated circuit.
As a method for chip size reduction, a method has been proposed in which a bonding pad, conventionally provided on the perimeter of a chip to avoid a region overlying an active region of a semiconductor substrate, is provided in an region overlying an active region of a semiconductor substrate (above the active region). (Hereinafter, a bonding pad provided in a region overlying an active region of a semiconductor substrate is referred to as an area pad.)
First, referring to
FIG. 8
, an example for forming an area pad in a semiconductor device with a two-layer wiring structure disclosed in Japanese Unexamined Patent Publication No. 1-91439/1989 (Tokukaihei 1-91439, published on Apr. 11, 1989) [Japanese Patent No. 2694252] will be described.
As shown in
FIG. 8
, a first Al wiring layer
102
is formed on a Si substrate (semiconductor substrate)
101
. On the first Al wiring layer
102
, inter-layer insulation films
103
to
105
(a plasma nitride film
103
, an NSG
104
, and a PSG
105
) are provided, then a through hole is formed through the inter-layer insulation films
103
to
105
by means of patterning and etching. A second Al wiring layer
106
is formed on the inter-layer insulation films
103
to
105
, and a final passivation film
107
is formed on the second Al wiring layer
106
.
On the final passivation film
107
, an opening section (pad opening section)
110
is formed above an active region (not shown). With this structure, an electrode pad is formed above the active region.
Therefore, in the foregoing semiconductor device, it can be considered that an exposed section
106
a
in the second Al wiring layer
106
(the part at the opening section
110
) functions as an electrode pad formed above the active region, that is, as an area pad.
Next, referring to
FIG. 9
, an example for forming a bonding pad in a semiconductor device with a three-layer wiring structure disclosed in Japanese Unexamined Patent Publication No. 4-62855/1992 (Tokukaihei 4-62855, published on Feb. 27, 1992) will be described.
A first wiring layer
203
is formed on a silicon substrate
201
on which an element (not shown) is provided, via an insulation film
202
. A second wiring layer
209
is formed on the first wiring layer
203
via inter-layer insulation films
205
to
207
(an insulation film
205
, a glass-coated film
206
, and an insulation film
207
). A third wiring layer
215
is formed on the second wiring layer
209
via inter-layer insulation films
212
to
214
. The third wiring layer
215
is connected with the second wiring layer
209
via through holes formed at predetermined positions in the inter-layer insulation films
212
to
214
. A protection film
210
is formed on the third wiring layer
215
.
Further, to relieve stress during wire bonding, a section
203
a
of the first wiring layer
203
, which is a section underlying a bonding pad section
215
a
(a section below the bonding pad section
215
a
), is processed to have a virtually same shape with that of the bonding pad section
215
a.
In the foregoing semiconductor device, the process for forming the bonding pad section
215
a
is completed by forming a hole
211
for bonding in the protection film
210
. Therefore, it can be considered that an exposed section in the third wiring layer
215
(the part at the hole
211
for bonding) becomes the bonding pad section
215
a
for electrically connecting the semiconductor device to an external section.
Further, a section
209
a
of the second wiring layer
209
, which is a section underlying the bonding pad section
215
a
(a section below the bonding pad section
215
a
), is divided into a plurality of parts by the inter-layer insulation films
212
to
214
. Therefore, in the structure disclosed in Japanese Unexamined Patent Publication No. 4-62855/1992, it can be considered that, in the second wiring layer
209
, there are a plurality of wires of the section
209
a
, which is the section underlying the bonding pad section
215
a
, in a region underlying the bonding pad section
215
a.
Next, referring to
FIG. 10
, an example for forming an area pa

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