Semiconductor memory device having auxiliary conduction...

Details Semiconductor memory device having auxiliary conduction... Semiconductor memory device having auxiliary conduction...

2000-04-13

2003-05-06

Lee, Eddie (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C365S051000, C365S063000, C365S104000, C365S182000, C365S230030

Reexamination Certificate

active

06559514

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a hierarchical bit line architecture having main and sub bit lines.
2. Description of the Related Art
Mask Read Only Memory (MROM) is a conventional semiconductor memory device which adopts a hierarchical bit line architecture. MROM includes a memory cell structure having two transistors (MOSFET) with different level threshold levels so as to store a binary digit. One of the two transistors has a low threshold level, i.e., a low voltage applied to the gate electrode can cause a sufficient current to flow through the transistor. The other has a high threshold level such that only a sufficiently high voltage applied to the gate electrode allows the current flow. The use of two transistors having low and high threshold levels, respectively, can realize the binary memory. The hierarchical bit line architecture is used to read the value of the binary digit stored in the corresponding transistor, and to integrate the memory cells in high density.
FIG. 2
is a circuit diagram representing an MROM with a hierarchical bit line architecture. As shown in
FIG. 2
, main bit lines MB
1
, MB
2
, . . . , etc. and sub bit lines SB
1
, SB
2
, . . . , etc. are arranged in a hierarchical structure. For example, the main bit line MB
1
is disposed between the odd-numbered sub bit line SB
1
and the even-numbered sub bit line SB
2
. One of memory cells M
1
, M
2
, . . . , etc., which includes a transistor, is disposed each between the adjacent two sub bit lines. The source of each of the memory cells M
1
, M
2
, . . . , etc. is connected to one of the adjacent two sub bit lines and the drain is connected to the other. The gates of the memory cells are connected to word lines WL
0
, . . . , WLn. The main bit lines MB
1
, MB
2
, . . . etc. are connected to sense circuits SA
1
, SA
2
, . . . , etc., respectively, and a charging circuit Ca, or are otherwise connected via transistors (MOSFET) Q
1
, Q
2
, . . . , etc. to GND. Each odd-numbered sub bit line is connected via a bank select transistor (MOSFET) BK
1
or BK
2
to a main bit line. The gates of the bank select transistors (MOSFET) BK
1
and BK
2
are connected to bank select lines BKL
1
and BKL
2
, respectively. Each even-numbered sub bit line is connected via a bank select transistor (MOSFET) BK
3
or BK
4
to a main bit line. The gates of the bank select transistors BK
3
and BK
4
are connected to bank select lines BKL
3
and BKL
4
, respectively.
In order to read the value of the memory cell M
4
, for example, the bank select line BKL
1
is activated so that the bank select transistor BK
1
is switched ON while the bank select line BKL
3
is activated so that the bank select transistor BK
3
is switched ON. This leads to formation of a current path from the charging circuit Ca to the main bit line MB
1
to the bank select transistor BK
1
to the sub bit line SB
3
. When the threshold of the memory cell M
4
is set to a low value, the activated word line WL
0
switches ON the memory cell M
4
. This allows a current to flow from the sub bit line SB
3
, to the memory cell M
4
, to the sub bit line SB
4
, to the bank select transistor BK
3
, to the main bit line MB
2
, to the transistor Q
1
, to GND. On the other hand, when the threshold of the memory cell M
4
is set to a high value, the activated word line WL
0
leaves the memory cell M
4
OFF. This does not allow a current to flow in the above-described path. The sense circuit SA
1
reads the binary digit stored in the memory cell M
4
by determining whether a current flows through the path or not.
FIG. 3
is a diagram illustrating a layout design of the semiconductor substrate on which the MROM shown in
FIG. 2
is provided.
In
FIG. 3
, a channel region Ch is provided in each of the bank select transistors BK
1
, BK
2
, . . . , etc. An auxiliary conduction region (diffusion region) H is connected via each of the bank select transistors BK
1
, BK
2
, . . . , etc. to each of the sub bit lines SB
1
, SB
2
, . . . , etc. Each of the bank select transistors BK
1
, BK
2
, . . . , etc. is connected via a contact hole CC of the corresponding auxiliary conduction region H to each of the main bit lines MB
1
, MB
2
, . . . , etc. The word lines WL
0
, . . . , WLn intersect the sub bit lines SB
1
, SB
2
, . . . , etc.
The main bit lines MB
1
, MB
2
, . . . , etc. are made of a low resistance material such as metal. The sub bit lines SB
1
, SB
2
, . . . , etc. are formed of a diffusion layer which enables formation of the source and drain of a transistor. Each memory cell uses two adjacent sub bit lines as a source electrode and a drain electrode, respectively, and one of the word lines WL
0
, . . . , WLn as a gate electrode in a way shown in FIG.
3
.
Here the bank select transistors BK
1
, BK
2
, etc. each have channel region Ch having a large width w
2
. The large-width channel regions Ch increase current flowing from the charging circuit to the memory cells M
1
, M
2
, . . . , etc. to GND, and the increased current can improve the performance of the bank select transistors BK
1
, BK
2
, . . . , etc. This leads to high-speed reading of data from the memory cells M
1
, M
2
, . . . , etc.
As shown in
FIG. 3
, the channel regions Ch of two adjacent bank select line s BK
1
, BK
2
, . . . , etc. face each other. For example, the channel region Ch of the bank select line BK
1
faces the channel region Ch of the bank select line BK
2
. The channel region Ch of the bank select line BK
3
faces the channel region Ch of the bank select line BK
4
. The width b between the bank select transistors, e.g. , between BK
1
and BK
2
or between BK
3
and BK
4
, is required to sufficiently isolate the bank selects transistors. The sufficient width b leads to an increase in the width a of a memory array, resulting in a large-sized chip.
To solve such a problem, Japanese Laid-Open Publication No. 6-104406 discloses an MROM which has a circuit structure and layout design as shown in
FIGS. 4 and 5
, respectively. Like numeral references refer to like parts in
FIGS. 2 through 5
.
As is apparent from
FIG. 4
, bank select transistors BK
2
-
1
and BK
2
-
2
are connected to each other in parallel and bank select transistors BK
3
-
1
and BK
3
-
2
are connected to each other in parallel. Each of the bank select transistors BK
2
-
1
and BK
2
-
2
has the same current supply performance (current amount per unit area) as that of the bank select transistor BK
2
shown in FIG.
2
. Each of the bank select transistors BK
3
-
1
and BK
3
-
2
has the same current supply performance as that of the bank select transistor BK
3
shown in FIG.
2
.
As is apparent from
FIG. 5
, the auxiliary conduction regions H (diffusion region) each have an H-shape. A sub bit line SB
1
is connected to an auxiliary conduction region H via the bank select transistors BK
2
-
1
and BK
2
-
2
. Similarly, sub bit line SB
2
is connected to an auxiliary conduction region H via the bank select transistor BK
4
. Sub bit line SB
3
is connected to an auxiliary conduction region H via the bank select transistor BK
1
. Sub bit line SB
4
is connected to an auxiliary conduction region H via the bank select transistors BK
3
-
1
and BK
3
-
2
. The auxiliary conduction regions H each are connected via a contact hole CC of an insulating layer (not shown) to one of the main bit lines MB
1
, MB
2
, . . . , etc.
Here the width w
1
of the channel region Ch of each of the bank select transistors BK
2
-
1
and BK
2
-
2
and the bank select transistors BK
3
-
1
and BK
3
-
2
is smaller than the width w
2
of the channel region Ch of each of the bank select transistors BK
2
and BK
3
shown in FIG.
3
. This prevents an increase in chip size.
The width W
1
of the channel region Ch of each of the bank select transistors BK
2
-
1
and BK
2
-
2
may be small. However, when the sum of the widths w
1
of the channel regions Ch of the bank select transistors BK
2
-
1
and BK
2
-
2
(i.e., w
1

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