Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-10-10
2003-01-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S189050, C365S194000
Reexamination Certificate
active
06507514
ABSTRACT:
TECHNICAL FIELD
The present invention is an integrated circuit memory chip useful to be packaged in either single or a multi-chip configuration wherein the same integrated circuit chip can be packaged together to form a higher density memory device.
BACKGROUND OF THE INVENTION
Integrated circuit memory chips are well known in the art. Typically, they are characterized by a memory array having a certain density, e.g. 64 M bits, 256 M bits, etc. They are typically assembled in a package with leads to the package serving as the interface to the final product.
Hybrid or multi-integrated circuit chips assembled into a single package are also well-known in the art. Typically, lead wires are attached to the integrated circuit chips to each other as well as to the leads to the assembled package. The advantage of a hybrid device is that a number of integrated circuit chips can be assembled into a single package thereby saving space on a printed circuit board. For NOR type memory, the user can use, for example, two 64 Mb devices to build a 128 Mb memory (2×64 Mb devices) or higher density such as 256 Mb (4×64 Mb devices) by adding discrete devices (TTL gates) to control CE pins of each 64 Mb devices. During operation, not more than one 64 Mb device is enabled due to separate control to each CE pin of the aggregated higher density memory. From the memory manufacturer's point of view, all 64 Mb devices look the same (both inside IC and package bonding) no matter what address space the 64 Mb device is eventually assigned by the user. But, there is an added cost of TTL gates to control CE pin.
Heretofore, when an integrated circuit memory chip of one generation having a certain capacity is designed, it is used for that capacity only. Thus, a 64 M bit integrated circuit chip is typically assembled into a single package and sold as a 64 M bit assembled device. To assemble a 128 M bit integrated circuit memory device, a 128 M bit integrated circuit chip has to be designed and produced. Thus, different types of chips must be manufactured and inventories of these chips must be kept.
Accordingly, it is one object of the present invention to save the inventory cost of producing different densities of integrated circuit memory chips.
SUMMARY OF THE INVENTION
In the present invention, an integrated circuit memory chip has an address port for receiving a first plurality of address signals for addressing a first memory space. The chip also has a data port. The chip further has a memory array addressable by a second plurality of address signals for receiving or providing a plurality of data signals from or to the data port. The second plurality of address signals addresses a second memory space where the second memory space is a portion of the first memory space. Finally, the chip has a control circuit for receiving the first plurality of address signals and for generating a delay signal in the event the first plurality of address signals addresses the memory array from the second memory space to a portion outside of the second memory space.
REFERENCES:
patent: 5602789 (1997-02-01), Endoh et al.
Lin Tien-Ler
Tsao Cheng-Chung
Gray Cary Ware & Freidenrich LLP
Hoang Huan
Integrated Memory Technologies, Inc.
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