Programming method of nonvolatile semiconductor memory device

Details Programming method of nonvolatile semiconductor memory device Programming method of nonvolatile semiconductor memory device

2000-10-25

2003-04-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185020, C365S185330, C365S185280

Reexamination Certificate

active

06556474

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a valid technique which is applied to a memory device of multivalued information in a nonvolatile semiconductor memory device and, more particularly, to a valid technique which is applied to a nonvolatile semiconductor memory device (simply referred to as a flash memory) in which a plurality of storage information can be electrically erased all at once.
2. Description of the Prior Art
A flash memory uses nonvolatile memory elements having a control gate and a floating gate for a memory cell which can comprise one transistor. Hitherto, as for the flash memory according to a method of injecting electrons in the floating gate, there are known a flash memory using a tunnel current which is supplied to the floating gate and a flash memory using hot electrons, etc.
An operation for injecting electrons in the floating gate and setting a threshold voltage of the memory cell to the high level is called as “write” and an operation for emitting electrons from the floating gate and setting the threshold voltage of the memory cell to the low level is called as “erase”.
According to the writing operation using the tunnel current, a drain area of the nonvolatile memory elements, a source area thereof, and a word line to which a control gate CG is connected are set to auxiliarily 0 V, 0 V, and 17 V, respectively, as shown in FIG.
5
A. The tunnel current injects electrons in a floating gate FG and the threshold voltage is set to the high level (logic “1”). In this case, in the memory cells not to be written (nonselected cell) which are connected to the same word line, a drain area thereof and a source area thereof are set to auxiliarily 5 V and 5 V, respectively. Thereby, the writing is prevented without generating the tunnel current. Referring to
FIG. 5A
, the left side of the diagonal line of 17/0 V for example denotes an applied voltage to a selected cell (in this case, the voltage of 17 V is applied to the control gate CG of the selected cell) and the right side thereof (in this case, the voltage of 0 V is applied to the control gate CG of the nonselected cell) denotes an applied voltage to the nonselected memory cell. In the other figures, applied voltages to the selected
onselected cell are also shown.
On the other hand, according to the writing operation using the hot electrons, a drain area of the nonvolatile memory elements, a source area thereof, and a word line to which the control gate CG is connected are set to auxiliarily 5 V, 0 V, and 10 V, respectively, as shown in FIG.
5
B. The hot electrons which are generated in a high electric-field area of a channel are injected in the floating gate FG and the threshold voltage is set to the high level (logic “1”). In this case, in the memory cell not to be written (nonselected cell) which are connected to the same word line, a drain area thereof and a source area thereof are set to auxiliarily 0 V. Thereby, a current is prevented from flowing in the memory cell. That is, the hot electrons are prevented to be generated, thereby preventing the writing.
In the erasing operation, when the above-mentioned writing using the tunnel current and the writing using hot electrons are performed, a drain area, a source area, a word line to which the control gate CG is connected are set to auxiliarily 0 V, 0 V, and −17 V, respectively, as shown in FIG.
6
. Thereby, electrons are emitted from a floating gate FG and the threshold voltage is set to the low level (logic “0”).
Accordingly, one-bit data is stored in one memory cell.
Then, data of two or more bits is stored in one memory cell so as to increase a memory capacity and this proposed concept is generally called as a “multivalued” memory. Conventional arts of the multivalued memory are disclosed, and ones in Japanese Patent Laid-Open Nos. 10-241380 and 10-27486 are labeled as a first conventional art and a second conventional art, respectively, hereinlater.
Herein, a description is given to a writing sequence, a time for writing, and an influence of word line disturbance which is caused by the writing when the writing using the tunnel current is described as an example in each of the cases according to the first conventional art and the second conventional art in the flash memory in which four-valued data can be stored in one memory cell by use of four threshold-voltages. It is assumed hereinafter that data corresponding to the four of the threshold voltage which is stored in the memory cell is labeled as follows, i.e., data which is in the erased state is labeled as “00” and data which is in the writing state is sequentially labeled as “01”, “10”, and “11” in order of the data of the threshold voltage nearer the erased state.
According to the first conventional art, if simultaneous writing data has “01”, “10”, and “11” in the writing starting from the erased state, the writing is executed at three steps of write #
1
, write #
2
, and write #
3
as shown in
FIGS. 3B
to
3
D.
A description is given to the sequence of the writing operation according to the first conventional art hereinlater with reference to
FIGS. 3A
to
3
E.
Incidentally, in the figures, a table shows write target data, memory cell data, disturbed state of the data which is written in the memory cells corresponding to four adjacent memory cells which are connected to the word line. Here, “++” shown in a column of the disturbed state denotes the word line disturbance by the writing of data having a threshold voltage higher than the threshold voltages which the memory cells have, and although not shown, “+” denotes the word line disturbance by the writing of data having a threshold voltage lower than the threshold voltages which the memory cells have (reference numerals in
FIGS. 1B
to
1
D,
FIGS. 2B
to
2
D, and
FIGS. 4B
to
4
D are the same as the foregoing).
First of all, in the initial state in
FIG. 3A
, all of the memory cells which become the write target are set to the erased state (storing data “00”) prior to the writing. A word line voltage Vw
0
is 0 V.
Next, in write #
1
in
FIG. 3B
, a word-line voltage is Vw
1
, and the data “01” is written to the memory cells to which the data “01”, “10”, and “11” is to be written. In this case, as shown in the figure, the drain voltage and the source voltage which are applied to the memory cells that become the selected cells when the writing is performed are 0 V, and the drain voltage and the source voltage which are applied to the memory cell that becomes the nonselected cell when the writing is performed are 5 V. This is the same hereinbelow.
Sequentially, in write #
2
in
FIG. 3C
, a word line voltage is Vw
2
and the data “10” is written to the memory cell to which the data “10” and “11” is to be written.
Finally, in write #
3
in
FIG. 3D
, a word line voltage is Vw
3
, and the data “11” is written to the memory cell to which the data “11” is to be written.
That is, as shown in
FIG. 3E
, this is a writing method whereby voltages are sequentially applied to the writing data “00”, “01”, “10”, and “11”, in other words, from the low word-line voltage VW
0
to the high word-line voltage Vw
3
in order of the steps of write #
1
to write #
3
so that the threshold voltages of the memory cells are set in distribution of the writing data “00”, “01”, “10”, and “11” which is write target data for the threshold voltages. Incidentally, in the
FIG. 3E
, Vwv
0
to Vwv
3
are word line voltages (threshold voltages) when verification is performed.
According to the second conventional art, the writing is executed at three steps shown in
FIGS. 4B
to
4
D.
A description is given to the sequence of the writing operation according to the second conventional art hereinafter with reference to
FIGS. 4A
to
4
E.
Incidentally, according to the second conventional art, the drain voltage and the source voltage which are applied to the memory cell that becomes the selected cell when the writing is performed are 0 V and the drain voltage and the sour

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