Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reissue Patent
1996-10-07
2003-03-25
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S238000, C438S692000, C438S633000, C216S006000
Reissue Patent
active
RE038049
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor circuit memory storage devices and more particularly to a process for fabricating three-dimensional stacked capacitor structures that may be used in such storage devices as high-density dynamic random access memories (DRAMs).
BACKGROUND OF THE INVENTION
In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of “stacked storage cell” design. With this technology, two or more layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining good dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A paper submitted by N. Shinmura, et al., entitled “A Stacked Capacitor Cell with Ring Structure,” Extended Abstracts of the 22nd International Conference on Solid State Devices and Materials, 1990, pp. 833-836, discusses a 3-dimensional stacked capacitor incorporating a ring structure around the main electrode to effectively double the capacitance of a conventional stacked capacitor.
The ring structure and its development is shown in FIGS.
1
(c) through
1
(g), pp. 834 of the article mentioned above. FIG.
1
(a), on the same page shows a bird's eye-view of storage electrodes. The storage node is formed by two polysilicon layers that form a core electrode encircled by a ring structure. Capacitor dielectric film surrounds the whole surface of the storage node electrode and then is covered with a third polysilicon layer to form the top capacitor electrode and completes the storage cell. This design can be fabricated using current methods and increases storage capacitance by as much as 200%.
Also,
in
a paper submitted by T. Kaga, et al., entitled “Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM's,” IEEE Transactions on Electron Devices. VOL. 38, NO. 2, February 1991, pp. 255-261, discusses a self-aligned stacked-capacitor cell for 64-Mb DRAM's, called a CROWN cell. The CROWN cell and its development are shown in FIGS.
7
(d) through
7
(f), pp. 258 of this article. The crown shaped storage electrode is formed over word and bit lines and separated by
a
an
oxide
itride insulating layer with the top insulating layer being removed to form the crown shape. Capacitor dielectric film surrounds the whole surface of the storage node electrode and the top capacitor electrode is formed to complete the storage cell.
The present invention develops an existing stacked capacitor fabrication process to construct and optimize a three-dimensional container stacked capacitor cell. The capacitor's bottom plate (or storage node plate) is centered over a buried contact (or node contact) connected to an access transistor's diffusion area. The method presented herein provides fabrication uniformity and repeatability of the three-dimensional container cell.
SUMMARY OF THE INVENTION
The invention is directed to maximizing storage cell surface area in a high density/high volume DRAM (dynamic random access memory) fabrication process. An existing capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The capacitor design of the present invention defines a stacked capacitor storage cell that is used in a DRAM process, however it will be evident to one skilled in the art to incorporate these steps into other processes requiring volatile memory cells, such as VRAMs or the like.
After a silicon wafer is prepared using conventional process steps, the present invention develops the container capacitor by etching a contact opening into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly by using Chemical Mechanical Polishing (CMP). This CMP step is selective such that oxide is removed with sufficient overetch and stops on the thin poly. The resuIting exposed poly is then removed to separate neighboring containers either through an isotropic wet poly etch or an additional CMP with the chemical aspect modified to now etch and selectively remove the poly and not the oxide. The two oxides, having different etch rates, are then etched by a single wet dilute BOE etch step, thereby leaving a free-standing poly container cell, with all the inside (high etch rate) oxide removed, that is equal in height to the depth of the original contact opening. In addition, a pre-determined amount of low etch rate oxide is removed
,
thereby leaving oxide surrounding the
,
container, poly for both structural support and process integration for further processing which requires oxide to be left above the word lines.
The present invention uses a higher etch-rate oxide inside the container to block the container poly etch. This high etch rate oxide is completely removed during oxide etch back. This protects the container during processing without adding photoresist and introducing extra processing steps or unwarranted contaminants. A standard CMP oxide etch is utilized that allows fabrication uniformity and repeatability across the wafer which cannot be achieved by resist filled container processes.
Another advantage of filling the container with high etch rate oxide is that the poly can be etched with a low cost, timed wet poly etch, while partially filled containers (as seen in FIG.
9
), due to inherent recession of resist
92
height (to allow for sufficient process margin), will not allow a wet poly etch without loss in cell height
93
, loss in uniformity and repeatability across the wafer's surface. Because this invention can be etched isotropically at poly etch, it avoids the recessing (overetch of the storage poly container
93
in
FIG. 9
) and splintering effects caused by a dry etch poly process.
As seen in
FIG. 10
, splintering effects
101
of storage node poly
93
result from a dry anisotropic etch (due to non-uniform etching of polycrystalline silicon
93
) because the plasma etch reacts faster along heavily doped grain boundaries. Splinters
101
later tend to ‘break off’ in subsequent processing leading to contamination particulates. The trenching of the poly leads to the side-walls of the poly container to be exposed, thus making it impossible to wet etch the oxide around the cell without translating the trenched poly horizontal portion of the etch into surrounding oxide
Dennison Charles H.
Walker Michael A.
Micro)n Technology, Inc.
Nguyen Tuan H.
Traskbritt
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