Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2001-06-29
2003-05-20
Tsai, Jey (Department: 2812)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C349S040000
Reexamination Certificate
active
06566902
ABSTRACT:
This application claims the benefit of Korean Patent Application No. P2000-79373, filed on Dec. 20, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly, to a testing structure in liquid crystal display.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmissivity of liquid crystal using an electric field to display a picture. The LCD typically includes a liquid crystal panel having liquid crystal cells arranged in a matrix configuration and a driving circuit for driving the liquid crystal panel. The liquid crystal panel also is provided with a plurality of pixel electrodes and a common electrode for selectively applying an electric field to each liquid crystal cell. The pixel electrodes typically are provided on a lower substrate for each liquid crystal cell, whereas the common electrode is integrally formed on the entire surface of an upper substrate. Each of the pixel electrodes is connected, via a source, an active region and a drain of a thin film transistor (TFT) used as a switching device, to one of a plurality of data signal lines. A gate terminal of each TFT positioned along a row of pixel cells is connected to one of a plurality of gate lines for applying pixel voltage signals from the data signal lines to pixel electrodes along the row.
After the LCD device having the above-described configuration is completed, a test process is performed to detect shorts and breakage of the signal lines, i.e., fault detection is carried out for the gate signal lines, the data signal lines, and the TFTs of the display panel.
To this end, the LCD device includes a structure for detecting a faulty line among the data signal lines and the gate signal lines. In particular, a testing pad is provided on the LCD device, and the data signal lines are divided into odd-numbered ones and even-numbered ones to test for faults in their structure.
FIG. 1
shows a related art LCD device structure for detecting a signal line fault. The LCD device includes a picture display portion
10
having liquid crystal cells arranged in a matrix configuration, gate pads
6
connected to gate lines GL, and data pads
2
connected to data signal lines DL. An odd-numbered detecting line ODDL is commonly connected via the data pads
2
to the odd-numbered data signal lines DL, an even-numbered detecting line EDDL is commonly connected via the data pads
2
to the even-numbered data signal lines DL, and electrostatic discharge (ESD) preventing circuits
4
are connected between a common electrode line CL and the data signal lines DL.
The picture display portion
10
includes the gate signal lines GL, the data signal lines DL, thin film transistors (TFT's) formed at each intersection between the gate lines GL and the data signal lines DL, and liquid crystal capacitors Clc connected to the TFT's. The liquid crystal capacitor Clc equivalently represents a liquid crystal cell including a common electrode and a pixel electrode provided at the TFT array panel that are opposed to each other with a liquid crystal therebetween. The liquid crystal capacitor Clc charges a data voltage input via the data signal line DL to drive a liquid crystal, thereby controlling a light transmissivity of the liquid crystal.
The ESD preventing circuit
4
is connected between the common electrode line CL and each data signal line DL, and is supplied with a common voltage Vcom. The ESD circuits typically consist of a plurality of thin film transistors and exhibit a low impedance at a high voltage to discharge an over-current during an ESD event. On the other hand, the ESD preventing circuit
4
has a high impedance under normal driving conditions so that driving signals applied via the data signal line are not affected.
The odd-numbered detecting line ODDL commonly connected to the odd-numbered data signal lines DL and the even-numbered detecting line EDDL commonly connected to the even-numbered data signal lines DL are used to test for faults in the data signal lines DL. More specifically, a specific signal pattern is applied to the odd-numbered detecting line ODDL and the even-numbered detecting line EDDL via a testing pad (not shown). A resistance difference between the odd-numbered detecting line ODDL and the even-numbered detecting line EDDL is measured to detect the presence of line faults, such as shorts, breakage, opens, and other defects in the data signal lines DL.
However, in the related art LCD device, since the data signal lines DL are connected in parallel between the odd-numbered detecting line ODDL and the even-numbered detecting line EDDL, an overall measured line resistance is decreased. A decrease in overall measured line resistance causes a decrease in a critical resistance value that is used for detecting line faults, and results in difficult and often unreliable detection of faults.
More specifically, as shown in
FIG. 1
, both the odd-numbered data signal lines DL commonly connected to the odd-numbered detecting line ODDL and the even-numbered data signal lines DL commonly connected to the even-numbered detecting line EDDL are connected to a single common electrode line CL by way of the ESD preventing circuits
4
. Thus, from the perspective of the common line CL and the ODDL and EDDL lines, the group of odd-numbered signal data lines and the group of even-numbered data signal lines form two groups of line resistances connected in parallel.
FIG. 2
schematically illustrates an equivalent circuit illustrating the above-described groups of parallel resistances. In particular,
FIG. 2
shows the odd-numbered data signal lines DL having line resistance components Rodd
1
to RoddN connected in parallel between the odd-numbered detecting lines ODDL and the common electrode line CL. Similarly, the even-numbered data signal lines DL have line resistance components Reven
1
to RevenN connected in parallel between the even-numbered detecting lines EDDL and the common electrode line CL. Since all the data signal lines DL are connected in parallel to a single common electrode line CL via the ESD circuits
4
, an appreciable line resistance difference between the odd-numbered detecting line ODDL and the even-numbered detecting line EDDL is difficult to obtain, and results in a low level detection critical resistance. If the detection critical resistance is low, it becomes extremely difficult to detect shorts or other faults in the data signal lines DL beyond the detection critical resistance.
Moreover, the increased number of data signal lines required for high-resolution pictures in an LCD device further decreases a measured line resistance difference because a greater number of signal lines are connected in parallel. Accordingly, the detection critical resistance is caused to farther decrease between the odd-numbered detecting line ODDL and the even-numbered detecting line EDDL. As a result, it becomes nearly impossible to detect signal line shorts and other related defects beyond the detection critical resistance.
Thus, there remains a need in the art for an LCD device structure that allows quick and accurate assessment of signal line integrity in an uncomplicated and cost effective manner.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a liquid crystal display structure for testing signal lines that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
One aspect of the present invention is a liquid crystal display device structure for testing a signal line in which an ability to detect a fault in a data signal line is improved by providing additional resistance to a signal line testing circuit.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and att
Bang Yong Ik
Kwon Keuk Sang
LG.Philips LCD Co. , Ltd.
Morgan & Lewis & Bockius, LLP
Tsai Jey
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