Static information storage and retrieval – Addressing
Reexamination Certificate
2001-07-17
2003-03-25
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
C326S105000
Reexamination Certificate
active
06538955
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-259108, filed Aug. 29, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a semiconductor integrated circuit that operates a power voltage by an increased voltage. More particularly, the present invention relates to a semiconductor integrated circuit adopted to improve hot carrier durability of an element to which such increased voltage is applied.
2. Description of the Related Art
Recently, in a DRAM (Dynamic Random Access Memory) that is a kind of semiconductor integrated circuit, a high-level signal in a word line is raised to a voltage higher than a power voltage, thereby achieving high speed data readout and write operations. The high-level signal of the word line signal is set to an increased voltage that is higher than the power voltage, whereby a high voltage is applied to a gate of a selection transistor that is connected to the word line during memory cell selection. In this manner, the conductive resistance of this selection transistor is lowered, and a greater readout or write current flows in the selection transistor as compared with a case in which the power voltage is applied to the gate of the selection transistor, whereby high speed data readout and write operations are achieved.
However, by using the increased voltage that is higher than the power voltage, there increases a substrate current that flows in a semiconductor substrate on which the DRAM is formed. In this manner, an increase in hot carrier is produced, and there occurs transistor degradation such as an increased threshold voltage of the transistor or a decrease in conductance.
In order to reduce such transistor degradation due to an increase in hot carrier and extend service life, there has been conventionally adopted a technique for connecting another transistor in series with a transistor to which the increased voltage is applied. The degradation of service life of the transistor due to a hot carrier is closely associated with a substrate current. That is, it is known that, if the substrate current is reduced by one digit, the service life increases by about three digits. The substrate current is represented by an exponential function of a voltage ‘Vds’ between a source and a drain. Therefore, in order to extend the service life of a transistor, it is most effective to alleviate the voltage conditions and reduce electrical field intensity applied to the transistor. A plurality of transistors are connected in series, whereby a voltage is divided by a plurality of these transistors, and a voltage applied to one transistor is reduced.
In general, an N-channel transistor is weaker than a P-channel transistor relevant to a hot carrier. Because of this, it is effective to connect transistors in series only to the N-channel side in a CMOS configured DRAM at which both of the P-channel and N-channel transistors are provided.
FIG. 1
shows an example of a conventional row decoder circuit in the CMOS configured DRAM, the circuit being provided as an example-of a semiconductor integrated circuit for which the above described hot carrier countermeasure is taken. In general, in a row decoder circuit, a plurality of decode circuits are arranged in an array manner in order to drive a plurality of word lines WL. Here, only one decode circuit for driving one word line WL is shown.
This row decoder circuit is composed of: a partial decode circuit
50
for decoding an address signal of a plurality of bits; two pre-driver circuits
51
and
52
cascade-connected so as to sequentially invert an output of this partial decode circuit
50
; a latch circuit
53
for latching an output of the partial decode circuit
50
and a word line driver circuit
54
for driving the word line WL based on an output of the pre-driver circuit
52
at a final stage.
The partial decode circuit
50
is of a pre-charge/discharge type, and is composed of a P-channel transistor P
11
and three N-channel transistors N
11
to N
13
. This partial decode circuit
50
outputs a decode signal based on a plurality of bits, i.e., address signals AX, AY, and AZ of three bits in this example, after a pre-charge period based on the pre-charge signal PREC has completed.
These two pre-driver circuits
51
and
52
are each composed of discrete P-channel transistors P
12
and P
13
, respectively, and two pairs of N-channel transistors N
14
and N
15
and N-channel transistors N
16
and N
17
, respectively. These circuits sequentially invert and supply outputs of the partial decode circuit
50
.
The word line driver circuit
54
is composed of one P-channel transistor P
14
and two N-channel transistors N
18
and N
19
. This circuit drives the word line WL upon receipt of an output of the pre-driver circuit
52
.
The latch circuit
53
is composed of one P-channel transistor P
15
and two N-channel transistors N
20
and N
21
. This latch circuit
53
latches a decode signal according to an original input address signal even after the input address signal level is changed after the pre-charge period in the partial decode circuit
50
has completed, and further, a decode output signal based on the input address signal has been determined. The latch circuit
53
is operatively controlled based on a pre-charge signal PREC and an output of the pre-driver circuit
51
.
Here, in order to set the high-level side voltage of a word line drive signal to an increased voltage that is higher than the power voltage, an increased voltage VPP to which a power voltage VCC is increased is applied to each source of each of the respective P-channel transistors in the pre-driver circuits
51
and
52
, the latch circuit
53
, and the word line driver circuit
54
.
In such a configured row decoder circuit, an increased voltage VPP is supplied as a power voltage of each of the pre-driver circuits
51
and
52
and the word line driver circuit
54
. Further, in order to reduce the electric field intensity applied to each of the N-channel side of the pre-driver circuits
51
and
52
and the word line driver circuit
54
, N-channel transistors N
14
, N
16
, and N
18
, each of which causes the increased voltage VPP to be applied to each gate, are connected in series, respectively, to N-channel transistors N
15
, N
17
, and N
19
.
In this way, the N-channel transistors N
14
, N
16
, and N
18
, each of which causes the increased voltage VPP to be applied to each gate, are connected in series, respectively, to the N-channel transistors N
15
, N
17
, and N
19
, whereby the maximum value of the voltage applied to the source of each of the N-channel transistors N
15
, N
17
, and N
19
becomes VPP-VthN (where VthN denotes a threshold value of an N-channel transistor), and a voltage ‘Vds’ applied between the drain and source of each of the N-channel transistors N
15
, N
17
, and N
19
is reduced by VthN as compared with the maximum value VPP of the voltage applied to the word line WL, as shown in FIG.
2
. In this manner, transistor degradation such as an increased threshold voltage or a decreased conductance based on an increase in substrate current as described previously is restrained.
However, in the word line driver circuit
54
, the transistor N
18
is connected in series to the N-channel transistor N
19
. Because of this, if an attempt is made to take a current drive force at the N-channel side so as to be equal to a case in which the transistor N
18
is not connected, a total size of the transistors at the N-channel side increases to four times its original size.
If the size of the N-channel side transistor that configures the word line driver circuit
54
increases, a vicious cycle is entered in which the pre-driver circuits
52
and
51
, used to drive the enlarged transistor, must also be enlarged, thus increasing the overall transistor size.
For example, when the N-channel side of the word line driver circuit
54
Banner & Witcoff , Ltd.
Ho Hoai
Kabushiki Kaisha Toshiba
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