Method of manufacturing MIS type FET semiconductor device with g

Details Method of manufacturing MIS type FET semiconductor device with g Method of manufacturing MIS type FET semiconductor device with g

1992-05-28

1994-01-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 42, 437 44, 437162, H01L 21265

Patent

active

052759601

ABSTRACT:
An MIS transistor includes insulating layers formed by the CVD method as gate insulating layers. The gate insulating layers by the CVD method are formed having a uniform film thickness on the channel region surface roughed by etching treatment or the like. The dielectric breakdown strength of the gate insulating layer is thus assured.

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Huang et al., "A MOS Transistor with Self-Aligned Polysilicon Source-Drain," IEEE Electron Device Letters, vol. 7, No. 5, May 1986, pp. 314-316.

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