Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-05-24
2003-04-22
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S633000, C438S720000
Reexamination Certificate
active
06551934
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating semiconductor device having a multilayer wiring structure. More particularly, the present invention relates to a technique for flattening a base layer on which the wiring is formed.
2. Description of the Related Art
In recent years, to increase the degree of integration in semiconductor integrated circuits, study for a constitution which increases not only the two-dimensional, but the three-dimensional degree of integration is being studied. A multilayer wiring is necessary to increase the three-dimensional degree of integration.
However, with an increase in the number of superposed layer of wiring, inevitably increases the surface roughness, and hence problems arise in which, for instance, relaxation of the design rule is required as the formation of layers progress to the upper layer.
As a method for overcoming the problem above, there is a known technique disclosed in Japanese Unexamined Patent Application in which the surface of a multilayer wiring is flattened.
It is still difficult, however, to flatten, as or a whole, an interlayer insulating film having surface irregularities and the electrodes and wirings that protrude from the contact hole formed on the interlayer insulating film.
For instance, when a multilayer structure as shown in
FIG. 3
comprising two layers of electrodes or wirings is formed, the surface thereof includes the irregularities of the interlayer insulating film
301
and the irregularities caused by the wirings or electrodes
302
to
304
having contacts with the lower wiring.
Such irregularities become obstacles in case a multilayer wiring is to be formed further thereon. However, it is difficult to wholly flatten such irregularities.
Further, from the problem of covering the inside of the contact holes for the electrodes
302
to
304
, disconnections and contact failure occur on the side planes inside the contact hole
300
.
To overcome the above problem, it is necessary to form the electrode material thick so enough as to fill the inside of the contact hole with a material constituting the electrode. However, if such a measure is taken, the electrode itself becomes a large protrusion, and brings about a novel problem ascribed thereto.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the problems of the irregularities being formed during the fabrication of a multilayer wiring, which are attributed to the presence of lower layer wiring. It is also an object of the present invention to provide a technique capable of flattening, as a whole, the irregularities of the interlayer insulating film and those attributed to the presence of the upper layer wiring itself.
According to an aspect of the present invention, there is provided a process for fabricating a semiconductor device having a multilayer wiring structure, characterized by comprising the steps of: forming a first wiring or electrode on a substrate; forming an insulating film which covers the first wiring or electrode; forming a contact hole to the first wiring or electrode through the insulating film; forming a wiring for contacting the first wiring or electrode inside the contact hole; and removing the protruded portion of the contact wiring and flattening the insulating film at the same time in an electrolytic solution by means of chemical mechanical polishing using the contact wiring as the anode.
According to another aspect of the present invention, there is provided a process for polishing the surface of a semiconductor device during its fabrication, characterized by comprising performing electrolytic polishing using the electrode of the semiconductor device as the anode while performing chemical mechanical polishing at the same time.
In accordance with still another aspect of the present invention, there is provided an apparatus for fabricating a semiconductor device, comprising: means for mechanically polishing the surface of a semiconductor device during its fabrication; and means for supplying electric current to the electrode of the semiconductor device.
In accordance with yet another aspect of the present invention, there is provided an apparatus for polishing the surface of a semiconductor device during its fabrication, characterized by comprising: means for performing chemical mechanical polishing; and means for supplying electric current to the electrode of the semiconductor device.
According to the present invention disclosed in the specification, an electrolytic solution having an electric resistance in a range of from 10
−3
to 10
10
(&OHgr;·cm)
−1
is used.
Also, electrically non-conductive particles having a granularity in a range of from number 4,000 to 10,000 are used as the chemical mechanical polishing material.
By using an electrically non-conductive material for the polishing material, the phenomenon of selectively removing the electrode can be prevented from occurring.
Further, by using an electrically non-conductive material as the polishing material, the problem of causing short circuit due to the presence of a conductive material during the fabrication steps of integrated circuits of a multilayer structure can be suppressed.
A material selected from the group consisting of diamond particles, alumina particles, carbon particles, and silica particles can be used as the electrically non-conductive material.
REFERENCES:
patent: 5391258 (1995-02-01), Brancaleoni et al.
patent: 5562529 (1996-10-01), Kishii et al.
patent: 5567300 (1996-10-01), Datta et al.
patent: 5575706 (1996-11-01), Tsai et al.
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5658806 (1997-08-01), Lin et al.
patent: 5767827 (1998-06-01), Kobayashi et al.
patent: 5807165 (1998-09-01), Uzoh et al.
patent: 5933204 (1999-08-01), Fukumoto
patent: 6242343 (2001-06-01), Yamazaki et al.
patent: 07-130848 (1995-05-01), None
patent: 7-193188 (1995-07-01), None
Teramoto Satoshi
Yamazaki Shunpei
Fish & Richardson P.C.
Ghyka Alexander
Semiconductor Energy Laboratory Co,. Ltd.
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