Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
2001-01-30
2003-05-20
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S347000, C257S349000, C438S151000
Reexamination Certificate
active
06566680
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the manufacture of semiconductor devices, and, more specifically, relates to the manufacture of semiconductor-on-insulator (SOI) tunneling junction transistor (TJT) devices.
BACKGROUND ART
Traditional semiconductor-on-insulator (SOI) transistor devices typically have a gate defining a channel interposed between a source and a drain formed within an active region of an SOI substrate. During an off-state of such an SOI transistor device electrons from the source are disposed to traversing the channel to the drain. This loss of electrons from the source to the drain is referred to as off-state leakage. Off-state leakage is controlled in such an SOI transistor device by increasing the off-state voltage to the gate electrode thereby reducing the size of the path between the source and drain through which the electrons traverse the channel. However, the increase in voltage to the gate electrode decreases the life span of the device as well as battery life in systems, which use batteries as the power source.
Therefore, there exists a strong need in the art for an SOI transistor device which reduces the off-state leakage, the voltage and the operating cost.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a tunneling junction transistor (TJT) device formed on a semiconductor-on-insulator (SOI) substrate. The TJT device includes a gate defining a channel interposed between a source and a drain formed within one of the active regions of the SOI substrate. At least one thin nitride layer is interposed between a portion of the channel and at least one of the source and the drain.
According to another aspect of the invention, the invention is a method of fabricating an SOI TJT device. The method includes the step of forming a gate on an SOI substrate. Additionally, the method includes the step of forming a nitride layer on the SOI substrate. The method further includes the step of forming the nitride layer interposed between at least a portion of a channel interposed between a source and a drain within one of the active regions.
According to another aspect of the invention, the invention is a method of fabricating an SOI TJT device as described immediately above. The method includes the additional steps of partially etching a semiconductor layer of the SOI substrate between the gate and the isolation trenches; oxidizing the etched semiconductor layer to repair an upper surface of the etched semiconductor layer and removing a resulting oxide layer. The method further includes the step of nitridizing the exposed upper surface of the etched and oxidized SOI substrate to form a thin nitride layer. Additionally, the method includes steps of forming a mask on the gate and a portion of the thin nitride layer and removing exposed portions of the nitride layer. Further, the method includes the steps of growing a semiconductor material on the exposed upper surface of the SOI substrate and the remaining plurality of resulting thin nitride layers and implanting dopants into the exposed semiconductor material and through a portion of the remaining plurality of resulting thin nitride layers to form a source and a drain.
According to another aspect of the invention, the invention is a method of fabricating an SOI TJT device. The method includes the step of forming a gate on an SOI substrate. The method includes the additional step of oxidizing the semiconductor layer to repair an upper surface of the semiconductor layer and removing a resulting oxide layer when forming the channel interposed between the source and the drain within one of the active regions. The method also includes the step of nitridizing the exposed upper surface of the oxidized SOI substrate to form a thin nitride layer. Further, the method includes the steps of forming a mask on the gate and a portion of the thin nitride layer and removing exposed portions of the nitride layer. Additionally, the method includes the steps of growing a semiconductor material on the exposed upper surface of the SOI substrate and the plurality of resulting thin nitride layers and implanting dopants into the exposed semiconductor material and through a portion the plurality of resulting thin nitride layers to form a source and a drain.
According to another aspect of the invention, the invention is an SOI TJT device. The TJT device includes a gate having at least one tunneling barrier interposed between a channel and at least one of a source and a drain formed within one of the active regions of the SOI substrate.
According to another aspect of the invention, the invention is a TJT device formed on a germanium-on-insulator (GOI) substrate. The GOI TJT device includes a gate having a channel interposed between a source and a drain formed within one of the active regions of the GOI substrate. Interposed between the channel and at least one of the source and the drain is a thin nitride layer.
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Advanced Micro Devices , Inc.
Booth Richard
Renner , Otto, Boisselle & Sklar, LLP
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