Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-12-18

2003-01-07

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S210130

Reexamination Certificate

active

06504789

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device that is capable of assigning the read time of data stored in memory cells. For example, the invention relates to a semiconductor memory device that controls the read time in terms of latency whose units are defined as the number of cycles of an externally applied clock.
2. Description of the Related Art
Among recent semiconductor memory devices, there is one that can externally assign the read time from the time that the read instruction is given until data stored in a memory cell is read out and is output from the semiconductor memory device. In particular, for synchronous mask ROM (synchronous mask read only memory), SDRAM (synchronous dynamic random access memory) and the like, whose operations are synchronized to the clock of the system that the semiconductor memory devices are used in, a term “latency”, which denotes the aforementioned read time by the number of clock cycles, is used.
By enabling latency to be externally assigned like this, it is possible to set the most appropriate read time according to the performance of the semiconductor memory device itself, the requirements of the system, and the user's application. That is to say, since the read time required by the semiconductor memory device is determined by the interrelationship between the semiconductor memory device and the system, there is a requirement that the read time be flexibly controlled depending on various conditions. For example, in recent years the operating frequencies of systems have been increasing, however, the reality is that the performance of semiconductor memory devices has not been keeping pace with the operating speed of systems. Consequently, in such a situation, it is necessary to bridge the performance gap that exists between systems and semiconductor memory devices, by assigning a large value of latency.
As an example of a semiconductor memory device used heretofore, synchronous mask ROM reads out data stored in memory cells as follows. Latency from CAS (column address strobe) signal active to valid data output, termed “CAS latency” is set externally from the synchronous mask ROM. Here, CAS latency may be abbreviated to “CL” in figures to be referred to in the descriptions hereunder and this description. In the case where reading is actually performed, first, a row address is assigned, the RAS (row address strobe) signal is activated, and the word line corresponding to the given row is address is activated.
Next, a column address is assigned, and the CAS signal is activated to select the digit line (also referred to as the bit line or data line) corresponding to the given column address. As a result, a unique memory cell that is specified by the row address and the column address is selected. Furthermore, as the CAS signal is active, the sense amplifier activation signal is made active to put the sense amplifier into an operational condition, and the sense amplifier senses the data stored in the memory cell via the selected digit line. The result sensed by the sense amplifier is output from the synchronous mask ROM via an output buffer or the like. Here, with conventional synchronous mask ROM, the sense amplifier activation signal is generated by utilizing a delay circuit and the like incorporated therein, and hence the period that the sense amplifier activation signal is valid is always constant.
Here,
FIG. 10
is a timing diagram showing the operation of the aforementioned conventional synchronous mask ROM. In the figure, timing from the time that the CAS signal becomes active to the time that data output is completed is shown for several values of CAS latency. Furthermore, “CLK” shown in the figure is a clock inside the synchronous mask ROM, which is synchronized to the system clock. For example, in the case where the CAS latency is “5”, the sense amplifier activation signal is activated [in other words, is set to “L” (low level)] immediately after the CAS signal is issued at the rising edge of the zeroth clock pulse of the clock CLK, and is deactivated [in other words, is set to “H” (high level)] immediately after the rising edge of the second clock pulse.
Then, data output is started around the falling edge of the fourth clock pulse, and at the rising edge of the fifth clock pulse when time corresponding to CAS latency “5” has passed since the CAS signal was given, a first data “D0” which is to be burst output becomes definite and is output outside as output data. Similarly to that mentioned above, also in cases other than CAS latency “5” due to different values of CAS latency, in the case where CAS latency is “6” through “8”, the value of data “D0” becomes definite at the rising edges of the sixth clock pulse through the eighth clock pulse. In such a way, with conventional synchronous mask ROM, whatever value is assigned to CAS latency, the valid period of the sense amplifier activation signal is always two cycles of clock CLK, which is constant.
In contrast to the abovementioned synchronous mask ROM, to give one example where the active period of the sense amplifier activation signal is varied depending on CAS latency, is an SDRAM that is disclosed in Japanese Unexamined Patent Application, First Publication No. 10-69770. This SDRAM is designed with a precondition that the operating frequency gets lower as the CAS latency value decreases. In this case, the period of each clock cycle becomes longer as the CAS latency value decreases. Accordingly, in the case where the CAS latency value is decreased, the active period of the column line select signal corresponding to the access period of the memory cells and the active period of a short signal corresponding to the equalizing period of the digit line are both lengthened.
That is to say, the arrangement is such that the ratio of the active period of the column line select signal to the active period of the short signal is always approximately constant, independent of CAS latency, and also the sum of these two periods is always equal to one cycle of the system clock, independent of CAS latency. To describe the abovementioned with specific numerical values, in the case where the CAS latency is “2” through “4”, the clock cycle times are “9 ns”, “7 ns” and “6 ns” respectively. At this time, the active periods of the column line select signal are “6 ns”, “4.6 ns” and “4 ns” respectively, and the active periods of the short signal are “3 ns”, “2.4 ns” and “2 ns” respectively.
From the above, with an existing synchronous mask ROM, a delay circuit and the like is used to generate the sense amplifier activation signal. Therefore, whatever value the CAS latency may be, the active period of the sense amplifier activation signal has been constant. Accordingly, with the abovementioned synchronous mask ROM, timing must be designed based on the smallest value of CAS latency (“5” in the range shown in FIG.
10
).
However, for values of CAS latency other than this, considering the case of CAS latency being “8” for example, data may be output for the first time at the rising edge of the eighth clock pulse. That is to say, the active period of the sense amplifier activation signal may not necessarily be two cycles, but may be longer than that. The greater the CAS latency value is, the longer the active period of the sense amplifier activation signal might be extended. In that sense, it can be said that with conventional synchronous mask ROM, the timing design was very inefficient.
If the active period of the sense amplifier activation signal is always constant, the operating margin of the sense amplifier when reading out data stored in memory cells is always the same whatever the value of CAS latency. By having an operating margin on the sense amplifier, it is possible to increase the operating frequency of the synchronous mask ROM by a corresponding amount. However, there is a problem in that with a synchronous mask ROM like that mentioned above, whatever the CAS latency may be set to, reading can in be perf

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