Method for controlling the electric field at a fed cathode...

Details Method for controlling the electric field at a fed cathode... Method for controlling the electric field at a fed cathode...

2001-06-08

2003-05-06

Wong, Don (Department: 2821)

Electric lamp and discharge devices: systems

Plural power supplies

Plural cathode and/or anode load device

C313S343000

Reexamination Certificate

active

06559602

ABSTRACT:

This patent document relates to field emission display (FED) devices described in the following patent documents filed concurrently herewith. The related patent documents, all of which are incorporated herein by reference, are.
U.S. patent application Ser. No. 09/877,365, of Russ, et al.; entitled METHOD OF VARIABLE RESOLUTION ON A FLAT PANEL DISPLAY;
U.S. patent application Ser. No. 091877,443, of Russ, et al.; entitled FIELD EMISSION DISPLAY UTILIZING A CATHODE FRAME-TYPE GATE AND ANODE WITH ALIGNMENT METHOD;
U.S. patent application Ser. No. 091877,379, of Russ, et al.; entitled METHOD FOR MAKING WIRES WITH A SPECIFIC CROSS SECTION FOR A FIELD EMISSION DISPLAY;
U.S. patent application Ser. No. 09/877,496, of Russ, et al.; entitled METHOD FOR ALIGNING FIELD EMISSION DISPLAY COMPONENTS;
U.S. patent application Ser. No. 09/877,371, of Russ, et al.; entitled CARBON CATHODE OF A FIELD EMISSION DISPLAY WITH IN-LAID ISOLATION BARRIER AND SUPPORT;
U.S. patent application Ser. No. 091877,510, of Russ, et al.; entitled METHOD FOR DRIVING A FIELD EMISSION DISPLAY; and
U.S. patent application Ser. No. 091877,509, of Russ, et al.; entitled CARBON CATHODE OF A FIELD EMISSION DISPLAY WITH INTEGRATED ISOLATION BARRIER AND SUPPORT ON SUBSTRATE.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to flat panel displays (FPDs), and more specifically to field emission displays (FEDs). Even more specifically, the present invention relates to the structural design of field emission displays (FEDs).
2. Discussion of the Related Art
A field emission display (FED) is a low power, flat cathode ray tube type display that uses a matrix-addressed cold cathode to produce light from a screen coated with phosphor materials.
FIG. 1
is a side cut-away view of a conventional FED. The FED
100
includes a cathode plate
102
and an anode plate
104
, which opposes the cathode plate
102
. The cathode plate
102
includes a cathode substrate
106
, a first dielectric layer
108
disposed on the cathode substrate
106
and several emitter wells
110
. Within each emitter well
110
is an electron emitter
112
. Thus, the electron emitters are formed as conical electron emitters, the shape of which aids in the removal of electrons from the tips of the electron emitters
112
. Each electron emitter
112
is generally referred to as a cathode sub-pixel. The cathode plate
102
also includes a gate electrode
114
integral with the cathode substrate
106
and disposed on the first dielectric layer
108
and circumscribing each emitter well
110
. In order to precisely align the gate electrode
114
with the electron emitters
112
, the emitter wells
110
are formed by cutting them out of the first dielectric layer
108
and the gate electrode
114
as formed on the cathode substrate
106
and then placing the electron emitters
112
within the emitter wells
110
. As such, the manufacture of the cathode plate
102
is difficult and expensive.
The anode plate
104
includes a transparent substrate
116
upon which is formed an anode
118
. Various phosphors are formed on the anode
118
and oppose the respective electron emitters
112
, for example, a red phosphor
120
, a green phosphor
122
and a blue phosphor
124
, each phosphor generally referred to as an anode sub-pixel.
The FED
100
operates by selectively applying a voltage potential between cathodes of the cathode substrate
106
and the gate electrode
114
, which causes selective emission from electron emitters
112
. The emitted electrons are accelerated toward and illuminate respective phosphors of the anode
118
by applying a proper potential to a portion of the anode
118
containing the selected phosphor. It is noted that one or more electron emitters may emit electrons at a single phosphor.
Additionally, in order to allow free flow of electrons from the cathode plate
102
to the phosphors and to prevent chemical contamination (e.g., oxidation of the electron emitters), the cathode plate
102
and the anode plate
104
are sealed within a vacuum. As such, depending upon the dimensions of the FED, e.g., structurally rigid spacers (not shown) are positioned between the cathode plate
102
and the anode plate
104
in order to withstand the vacuum pressure over the area of the FED device.
In another conventional FED design illustrated in
FIG. 2
, an FED
200
further includes a second dielectric layer
202
disposed upon the gate electrode
114
and a focusing electrode
204
disposed upon the second dielectric layer
202
. In operation, a potential is also applied to the focusing electrode
204
. This potential is selected to collimate the electron beam emitted from respective electron emitters
112
. Thus, the focusing electrode
204
concentrates the electrons to better illuminate a single phosphor, i.e., the emitted electrons are focused. However, in order to reduce the spread of electrons, a separate focusing structure (i.e., focusing electrode
204
) formed over the gate electrode
114
and that is integral to the cathode substrate
106
is required.
FIG. 3
illustrates a cut-away perspective view of the conventional FED
100
of FIG.
1
. As shown, the gate electrode
114
and the first dielectric layer
108
form a grid in which the generally circular-shaped emitter wells
110
are formed. In fabrication, the first dielectric layer
108
and the gate electrode
114
are formed over the cathode substrate
106
. The emitter wells
110
are formed by etching or cutting out the first dielectric layer
108
and the gate electrode
114
. The conical-shaped electron emitters
112
are then deposited into the emitter well
110
.
Advantageously, the conventional FED provides a relatively thin display device that can achieve CRT-like performance. However, the conventional FED is limited by the pixelation of the device. For example, since there are a fixed number of electron emitters
112
and phosphors aligned therewith, the resolution of the conventional FED is fixed. Furthermore, the manufacture of conventional FEDs has proven difficult and expensive. Additionally, while driving the conventional FED, i.e., applying the proper potential between the gate electrode and the electron emitters
112
, cross-talk is a common problem.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a device and method for controlling the electric field at a cathode sub-pixel of an improved field emission display (FED) having a novel structural design.
In one embodiment, the invention can be characterized as a device for controlling an electric field at a cathode sub-pixel region of a field emission display comprising a cathode substrate having a plurality of emitter lines formed on the cathode substrate. Also included is a gate frame having a plurality of gate wires positioned over respective the plurality of emitter lines. Each of the plurality of gate wires has a cross section shaped to produce an electric field between adjacent ones of the plurality of gate wires that is substantially uniform and substantially flat across the cathode sub-pixel region of respective ones of the plurality of emitter lines. The cathode sub-pixel region is defined as a portion of each of the plurality of emitter lines in between the adjacent ones of the plurality of gate wires.
In another embodiment, the invention can be characterized as a method of controlling an electric field of a field emission display, and a means for accomplishing the method, the method comprising the steps of: applying a potential between adjacent gate wires of a gate frame positioned above an emitter line of the field emission display and the emitter line, wherein a cathode sub-pixel region is defined as a portion of the emitter line in between the adjacent gate wires; and producing an electric field between the adjacent gate wires and the cathode sub-pixel region, wherein a cross section of the adjacent gate wires is shaped to cause the electric field to be substantially uniform and substantially f

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