Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-01-08
2003-04-15
Smith, Matthew S. (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S238000, C438S649000, C257S069000
Reexamination Certificate
active
06548885
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same and, more particularly, to a technique which is effective if applied to a semiconductor integrated circuit device having a SRAM (i.e., Static Random Access Memory).
The SRAM, as acting as a semiconductor memory device, is equipped with memory cells a memory cell which is disposed at an intersection between a word line and a pair of complementary data lines and composed of a flip-flop circuit and two transfer MISFETs (i.e., Metal Insulator Semiconductor Field Effect Transistors).
The flip-flop circuit of the memory cell of the SRAM is constructed as an information storage unit for storing information of 1 bit. This flip-flop circuit of the memory cell is exemplified by a pair of CMOS (i.e., Complementary, Metal Oxide Semiconductor) inverters. Each of the CMOS inverters is composed of n-channel type drive MISFETs and p-channel load MISFETs. On the other hand, transfer MISFETs are of the n-channel type. In short, this memory cell is of the so-called “CMOS (i.e., Full Complementary Metal Oxide Semiconductor)” using the six MISFETs. Incidentally, the complete CMOS type SRAM, which is formed over the principal surface of the semiconductor substrate with the drive MISFETs, the load MISFETs and the transfer MISFETs, will be called the “bulk CMOS type SRAM”. This bulk CMOS type SRAM is disclosed, for example, on pp. 590 to 593 of IEDM (i.e., International Electron Device Meeting), Technical Digest, 1985.
In the SRAM of this kind, the paired CMOS inverters constituting the flip-flop circuit have their input/output terminals crossly connected with each other through a pair of wiring lines (as will be called the “local wiring lines”). One of the CMOS inverters has its input/output terminals connected with the source region of one of the transfer MISFETs, and the other CMOS inverter has its input/output terminals connected with the source region of the other transfer MISFET. One of the complementary data lines is connected with the drain region of one of transfer MISFETs, and the other complementary data line is connected with the drain region of the other transfer MISFET. With the individual gate electrodes of the paired transfer MISFETS, there is connected word lines, by which are controlled the ON/OFF of the transfer MISFETs. In the above-specified Publication, the local wiring lines are formed by a self-aligning silicide process. This silicide process per se is disclosed on pp. 118 to 121 of IEDM, Technical Digest, 1984.
SUMMARY OF THE INVENTION
As the capacity of a semiconductor memory device grows larger and larger according to the progress of the miniaturizing technique in recent years, the area to be occupied by the memory cell of the aforementioned bulk CMOS type SRAM grows smaller and smaller. However, when the area occupied by the memory cell is reduced, the storage node capacity (i.e., the pn junction capacity or gate capacity parasitic to the aforementioned storage nodes A and B) of the memory cell is reduced to reduced the amount of stored charge.
As a result, the resistance to the information inversion (i.e., the so-called “&agr; ray soft error”) of the memory cell due to the &agr; ray having irradiated the surface of the semiconductor chip is lowered to make it difficult to retain the safe operation of the memory cell. In order to promote the miniature structure without deteriorating the stable operation of the memory cell, therefore, the counter-measures for retaining the amount of stored charge are indispensable.
More specifically, if the memory cell is irradiated with the &agr; ray which is emitted when a radioactive element, as contained in a trace amount in a package or resin material used for sealing the memory cell, such as uranium or thorium disintegrates, electron/hole pairs are produced along the range of the a ray to immigrate into the pn junction forming the storage node so that the information of the memory cell is broken. This phenomenon is called the “soft error”. In the bulk CMOS type SRAM of the prior art, because of the large memory cell area, the capacity of the storage node itself, as composed of a pn junction capacity or a gate capacity, and the driving ability of the load MISFETs is so high that the storage node can be stored with charge sufficient for compensating the charge loss due to the &agr; ray. If the memory cell area is miniaturized, however, the amount of charge to be stored in the storage node is also reduced to raise a problem that the resistance of the memory cell to the irradiation of the &agr; ray is deteriorated.
Specifically, we have found that new counter measures for retaining the charge storing amount of the memory cell is indispensable in the bulk CMOS type SRAM, too, for further miniaturizing the memory cell of the SRAM.
An object of the present invention is to provide a technique capable of improving the resistance to the soft error by increasing the storage node capacity of the memory cell of the SRAM.
Another object of the present invention is to provide a technique capable of miniaturizing the memory cell of the SRAM.
Another object of the present invention is to provide a technique capable of operating the memory cell of the SRAM at a high speed and at a low voltage.
Another object of the present invention is to provide a technique capable of improving the production yield and reliability of the memory cell of the SRAM.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
The representative ones of the invention to be disclosed herein will be summarized in the following.
(1) A semiconductor integrated circuit device including a SRAM having a memory cell comprising: a flip-flop circuit composed of a pair of CMIS inverters having drive MISFETs and load MISFETs; and a pair of transfer MISFETs connected with a pair of input/output terminals of said flip-flop circuit, wherein a first conducting layer is formed over the principal surface of a semiconductor substrate to form the individual gate electrodes of said drive MISFETS, said load MISFETs and said transfer MISFETs, wherein a second conducting layer is formed over said first conducting layer to form a pair of local wiring lines for connecting the individual input/output terminals of said paired CMIS inverters, wherein a third conducting layer is formed over said second conducting layer to form a reference voltage line to be connected with the source region of said drive MISFETS, and wherein said reference voltage line is arranged to be superposed over said paired local wiring lines.
(2) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein said local wiring lines are partially extended over the gate electrode of said drive MISFETs, said load MISFETs or said transfer MISFETS.
(3) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein said local wiring lines are partially extended over a semiconductor region constituting the input/output terminals of said CMIS inverters.
(4) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein there is formed over said reference voltage line a fourth conducting layer which is made of a conducting material having a lower resistance than that of said third conducting layer constituting said reference voltage line, for supplying a reference voltage, and wherein said fourth conducting layer and said reference voltage line are electrically connected through at least one connection hole which is formed in each memory cell.
(5) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein the connection hole for connecting said fourth conducting layer and said reference voltage line and the connection hole for connecting the reference voltage line and the source region of said drive MISFETs are spaced from each other.
(6) In the aforementioned SRAM, a semiconductor integrated circuit devic
Fukami Akira
Iida Masaya
Ikeda Shuji
Kikushima Ken'ichi
Mitani Shinichiro
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lee Calvin
Smith Matthew S.
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