Column decoder circuit for page reading of a semiconductor...

Details Column decoder circuit for page reading of a semiconductor... Column decoder circuit for page reading of a semiconductor...

2001-02-27

2003-01-14

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S230020, C365S230030, C365S231000

Reexamination Certificate

active

06507534

ABSTRACT:

TECHNICAL FIELD
The present invention refers to a column decoder circuit for page reading of a semiconductor memory.
BACKGROUND OF THE INVENTION
It is known that reducing the time for reading semiconductor memories currently represents a problem of considerable importance.
In particular, it is known that the data contained in a memory are not immediately available as soon as a reading operation is requested. In fact, it is necessary to wait for a latency time required for decoding the addresses of the memory words to be read (addressing of the memory), for selecting the memory cells, and transferring the information on a data bus.
Column decoder circuits have thus been studied that enable simultaneous reading of a number of memory words, if these are set in consecutive memory locations (the reading of series of consecutive memory words, known as “burst-mode” reading, is in fact a frequent case). The memory words read are supplied in succession on a data bus at every clock cycle, so as to eliminate or reduce the latency times.
For greater clarity, reference is made to
FIG. 1
, which shows a column decoder circuit
1
of a known type, in particular having 128 columns per bit and allowing simultaneous reading of four memory words having consecutive addresses (memory pages). The column decoder circuit
1
, belonging to a semiconductor memory, comprises a first level decoder stage
2
, a second level decoder stage
3
, and a plurality of bit selection stages
4
. In particular, the bit selection stages
4
are equal in number to the bits forming a memory word (for example,
16
).
The first level decoder stage
2
has an input connected to an address bus
5
, from which it receives two first level address bits, and is connected at the output to a first level bus
7
to supply four first level signals YO
0
, . . . , YO
3
, each having a selection value and a deselection value.
The second level decoder stage
3
has an input connected to an address bus
5
, from which it receives three second level address bits, and is connected at the output to a second level bus
8
to supply eight second level signals YN
0
, . . . , YN
7
, each having a selection value and a deselection value.
In particular, during reading, a single first level signal YO
0
, . . . , YO
3
and a single second level signal YN
0
, . . . , YN
7
at a time are set at the selection value, while all the other first level and second level signals have the deselection value.
Each of the bit selection stages
4
has first level inputs, connected to the first level bus
7
, second level inputs, connected to the second level bus
8
, and third level inputs, connected to the address bus
5
, from which they receive two third level address bits. In addition, each of the bit selection stages
4
is connected to a respective group of bit lines
10
of a memory array (not shown), and has an output connected to a data bus
11
. Each group of bit lines
10
comprises, for example, 128 bit lines
10
, identified in
FIG. 1
by a progressive number between 0 and 127, corresponding to a column address of a memory word.
FIG. 2
shows in greater detail a block diagram of a bit selection stage
4
, which comprises first level selector stages
15
, second level selector stages
16
, column amplifiers
14
, also referred to as sense amplifiers, and a multiplexer
12
.
Each first level selector stage
15
is connected to the first level bus
7
supplying the first level signals YO
0
, . . . , YO
3
, and to four bit lines
10
. In particular, the bit lines
10
connected to a same first level selector stage
15
have column addresses k, k+32, k+64,k+96(k=0, 1, . . . , 31).
Each second level selector stage
16
is connected to the second level bus
8
, supplying the second level signals YN
0
. . . , YN
7
, and to eight first level selector stages
15
.
The multiplexer
12
is connected to the second level selector stages
16
via the column amplifiers
14
and pass transistors
18
. In addition, the multiplexer
12
is connected to the address bus
5
, supplying the third level address bits, and has an output connected to the data bus
11
.
FIG. 3
shows a circuit diagram of the bit selection stage
4
shown in FIG.
2
.
According to the values of the first level signals YO
0
. . . , YO
3
, each first level selector stage
15
selects and connects one of the bit lines
10
to the respective second level selector stage
16
. For example, all the lines having column address k+32 (wherein k=0, 1, . . . , 31) are selected. Likewise, each second level selector stage
16
, according to the values of the second level signals YN
0
. . . , YN
7
, selects and connects a first level selector stage
15
to the respective column amplifier
14
. In practice, four bit lines
10
having consecutive addresses are selected simultaneously, so that the content of four memory cells (not shown) connected to the selected bit lines
10
is available at the inputs of the multiplexer
12
. If it is necessary to read one or more memory pages, in successive clock cycles, the multiplexer
12
sets the data present on its own inputs in sequence on the data bus
11
.
In known column decoder circuits, however, it is disadvantageous that simultaneous reading of four memory words is possible only if the address of the first memory word to be read can be divided by four. Otherwise, it would be necessary to have available, for each second level selector stage
16
, a set of independent values of the second level signals YN
0
. . . , YN
7
, while there are present a single second level decoder stage
3
and a single second level bus
8
. Suppose, for example, that it is required to read memory words having column addresses
1
,
2
,
3
and
4
. The bit lines
10
for the column addresses
1
,
2
and
3
can be selected by setting the second level signal YN
0
at the selection value, which, however, selects the bit line
10
for the column address
0
, instead of the one having column address
4
(FIGS.
2
and
3
). Consequently, in this case it is possible to read only three valid memory words simultaneously.
SUMMARY OF THE INVENTION
According to principles of the present invention, a column decoder circuit is provided that enables reading of memory pages independently of the initial column address. A column decoder circuit is provided for page reading of a semiconductor memory that includes a circuit.


REFERENCES:
patent: 5179687 (1993-01-01), Hidaka et al.
patent: 5285421 (1994-02-01), Young et al.
patent: 5353427 (1994-10-01), Fujishima et al.
patent: 5500819 (1996-03-01), Runas
patent: 5696917 (1997-12-01), Mills et al.
patent: 5835436 (1998-11-01), Ooishi
patent: 5901086 (1999-05-01), Wang et al.
patent: 5901105 (1999-05-01), Ong et al.
patent: 5999451 (1999-12-01), Lin et al.
patent: 6175532 (2001-01-01), Ooishi
patent: 6212111 (2001-04-01), Wright
patent: 6233195 (2001-05-01), Yamazaki et al.

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