Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-02-14
2003-01-07
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000
Reexamination Certificate
active
06503836
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method and apparatus for manufacturing a semiconductor device having an interlayer insulating film, and more particularly, to a method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP (Chemical Mechanical Polishing) process.
2. Description of the Background Art
An interlayer insulating film of a semiconductor device is formed by heat-treating an insulating film of BPTEOS (Boro-Phospho-Tetra-Ethyl-Ortho-Silicate), BPSG (Boro-Phospho-Silicate-Glass) or the like and flattening the resultant film by the CMP process. Degraded flatness of the interlayer insulating film causes contact misalignment or the like, thereby making it difficult to realize miniaturization of the semiconductor device. Therefore, with the progress in miniaturization of the semiconductor devices, some proposals have been made to improve the flatness of the interlayer insulating film.
For example, a method for manufacturing a semiconductor device having an interlayer insulating film of which flatness is improved in consideration of underlying projections and impurity concentration has been proposed (Japanese Patent Laying-Open No. 11-154677). In
FIG. 15
, a semiconductor substrate
101
has projections
106
such as gate electrodes and interconnections at its surface, and an interlayer insulating film is deposited thereon. The surface of the interlayer insulating film includes small bumps reflecting individual projections
106
, and large, gentle bumps reflecting the density of the projections such as the gate electrodes. In general, in flattening the interlayer insulating film, such small bumps are naturally polished away while the large bumps are being polished.
In this method, as shown in
FIG. 15
, the interlayer insulating film has a two-layer structure of a high-concentration impurity layer
122
and a low-concentration impurity layer
102
. High-concentration impurity layer
122
having a thickness that is equal to or larger than the height of projections
106
is formed at a surface-layer region of the interlayer insulating film, so that high-concentration impurity layer
122
is distinguished from low-concentration impurity layer
102
formed thereunder. It should be understood that the interface between high-concentration impurity layer
122
and low-concentration impurity layer
102
as well as the surface of high-concentration impurity layer
122
both include bumps reflecting projections
106
. When the interlayer insulating film is polished by the CMP process, high-concentration impurity layer
122
is first polished. As shown in
FIG. 16
, at a stage t
1
of the process, polishing of high-concentration impurity layer
122
is completed as well as polishing of low-concentration impurity layer
102
is started in a projecting portion corresponding to a high projection density. This is because such a projecting portion is polished at a higher rate. At stage t
1
, however, high-concentration impurity layer
122
is still being polished in a recessed portion corresponding to a low projection density, because such a recessed portion is polished at a lower rate. In other words, at stage t
1
, a surface including both low-concentration impurity layer
102
(i.e., a region corresponding to the high projection density) and high-concentration impurity layer
122
(i.e., a region corresponding to the low projection density) is polished. A portion having projections
106
thereunder is polished at a higher rate than a portion having no projection
106
thereunder. Moreover, since high-concentration impurity layer
122
is soft, it is polished at a higher rate than low-concentration impurity layer
102
. Therefore, at stage t
1
as shown in
FIG. 16
, the surface including both low-concentration impurity layer
102
and high-concentration impurity layer
122
is polished, but both regions are polished at approximately the same rate. Accordingly, when high-concentration impurity layer
122
has been polished away from the polish surface, a highly flat interlayer insulating film can be obtained.
In order to suppress the impurity diffusion, reduction in time and temperature of the heat treatment is an essential requirement for the recent semiconductor devices. Therefore, RTP (Rapid Thermal Process) is used for the heat treatment. However, such reduction in temperature is strongly required even in the RTP that uses a higher heating temperature than that of a furnace-anneal process. Such a short-time RTP has a large temperature variation between the portions of a heat-treated semiconductor device (wafer). Therefore, a concentration distribution of impurities such as B (boron) and P (phosphorus) within the interlayer insulating film is varied, thereby inevitably resulting in a non-uniform impurity-concentration distribution. Accordingly, the interlayer insulating film has undesirably degraded flatness after the subsequent CMP process. It should be noted that, in the specification, the heat treatment refers to anneal processes including RTP and furnace anneal.
The above-mentioned phenomenon is exemplarily described for a semiconductor device including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with reference to
FIGS. 17
to
20
.
FIG. 17
is a cross-sectional view illustrating processes of degassing (outgassing) and pre-flattening an interlayer insulating film in the RTP. In
FIG. 17
, an interlayer insulating film
102
is formed on a semiconductor substrate
101
including a semiconductor-element portion such as a gate. A semiconductor device including interlayer insulating film
102
is heated by an RTP apparatus
103
.
FIG. 18
is an enlarged view of a cross section taken along the line Y
1
-Y
2
of FIG.
17
. At the surface of the semiconductor substrate
101
, source/drain regions
105
are formed with a channel region therebetween, and gate electrodes
106
are formed on the respective channel regions. An element-isolating region
104
is formed between the elements. The interlayer insulating film
102
has small bumps at its surface due to the projections of the underlying gate electrodes
106
. The purpose of the RTP is to activate impurities in a region of the semiconductor substrate as well as to bake the interlayer insulating film.
FIG. 19
is a diagram showing impurity-concentration distribution profiles along the line X
1
-X
2
(
FIG. 18
) at the surface of interlayer insulating film
102
before and after the RTP. In
FIG. 19
, an impurity-concentration distribution E
1
before anneal is flat, whereas an impurity-concentration distribution E
2
after the RTP is raised in the center of the line X
1
-X
2
. A wavelength of such a variation in the impurity-concentration profile is much larger than that of the profile of the bumps produced by gate electrodes
106
of
FIG. 18. A
region having an increased impurity concentration has reduced hardness. Therefore, when the interlayer insulating film having impurity-concentration distribution E
2
of
FIG. 19
is subjected to the CMP process, the resultant interlayer insulating film has a (film-thickness distribution G
2
as shown in FIG.
20
. More specifically, even if the interlayer insulating film has a flat film-thickness distribution G
1
before the CMP process, the interlayer insulating film subjected to the CMP process has film-thickness distribution G
2
that is reduced in the center. This is because a region having a high impurity concentration is polished at a high rate. It is difficult to obtain a uniform film thickness by the CMP process. Therefore, the impurity-concentration distribution must be made uniform before the CMP process.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP process by making uniform a non-uniform impurity-concentration distribution resulting from heat treatment correspondin
Kamoshima Takao
Matsuoka Takeru
Yamashita Takashi
Chen Kin-Chan
Mitsubishi Denki & Kabushiki Kaisha
Utech Benjamin L.
LandOfFree
Method and apparatus for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for manufacturing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3058699