Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-03-09
2003-01-14
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06507204
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for testing a semiconductor element or device, and more particularly to a method for testing a highly reliable and high-yield semiconductor device and its electric characteristic by doing an efficient test of the electric characteristic of the semiconductor element in a semiconductor manufacturing process, such as a probing test and a burn-in test to be done for a wafer.
A process of manufacturing a semiconductor such as an IC and an LSI may be generally divided into a first process from the start to the formation of an integrated circuit on the surface of a silicon wafer, and a second process from the end of the first process to the separation of the silicon wafer into chips and sealing of each chip by resin or ceramics.
In the semiconductor device manufactured in the process, the electric characteristic of each circuit contained in the semiconductor is tested for checking if each chip is defective.
This electric characteristic test may be roughly divided into a probing test for checking if the conduction between the circuits is defective, a burn-in test for acceleratively separating good circuits from defective ones by applying thermal and electric stress onto the circuits at a high temperature of about 150° C., and a final test for testing the circuits through the use of a high frequency. In the final test to be done with the high frequency, it is desirous to use a testing system of fast operation in which the fast device is tested by means of a super high frequency.
The foregoing various kinds of testing methods just need a similar connecting means between a wafer or a chip to be tested and an external testing system. Concretely, a conductive minute probe is mechanically pressed on an electrode pad made of aluminum alloy or another alloy, the electrode pad being patterned on the wafer to be tested at pitches of several tens to one hundred and several tens micro millimeters, several tens to one hundred and several tens micro millimeters per side, and in thickness of about 1 micro millimeter.
Recently, in place, a system for testing bare chips being formed on a wafer is designed, because some customers are requesting bare chips not to be packaged such as a MCM (Multi Chip Module). The technology of doing a burn-in test for a wafer has been described in JP-A-8-148533. This burn-in test is executed so that spots corresponding to electrode pads of a wafer to be tested are electrically connected with electrode pads of a testing substrate made of silicon through an anisotropic conductive film laid therebetween, and the probes are taken out onto the wafer to be tested through through-holes formed in the testing substrate. The electrical communication with an external equipment is performed through wires.
The testing method of the semiconductor device as mentioned above in the prior arts has the following problems.
At first, each cantilever with a probe formed of a silicon system material is junctioned with the corresponding insulated substrate surface. A troublesome operation is therefore required for positioning and fixing each probe at high precision. It means that this construction has difficulty in narrowing the pitch of the electric pads, thereby possibly lowering a manufacturing yield. Moreover, after each probe is junctioned on the insulated substrate surface, it is presumed that the heights of the probes are so variable that the probes cannot be formed at a constant height. Since the wires led from the probes are routed peripherally, the wires for electrically connecting the tips of the probes with an external testing system are formed on the substantially same level with the probe forming surface of the substrate. This inevitably needs to form all the external connecting terminals concentratively around the outer periphery of the substrate. It means that the area where the external connecting terminals are to be formed is limited. As a result, it becomes difficult to electrically connect lots of probes with the external. This inhibits to test a large area of the wafer to be tested at a time, that is, all the electrode pads of the wafer to be tested at a batch. Further, it is also presumed that the wires are made longer and thereby the measurement with a high frequency is made difficult.
In the conventional construction in which the routing of the wires is formed in the upper portion, the wires are led from the probes through the through holes. However, the wires to the piezoelectric elements are assembled by using plural substrates, so that the conduction is made defective by the positional shift of the wire between the substrates and the manufacturing yield is also made lower.
In the construction disclosed in JP-A-8-148533, the conduction between the electrode pads formed on the testing substrate and those formed on the wafer to be tested is through the anisotropic conductive film. Hence, it is presumed that the test of the device patterned at a narrow pitch is made difficult.
The foregoing prior arts do not consider the electrostatic capacity of the silicon. It means that the test of the fast device of 200 MHz or higher is made substantially impossible. In particular, the prior arts are constructed so that the through holes are formed in the silicon substrate. Thereby, this construction has difficulty in forming an insulating film to be thick on the side of the each through hole, and increases the electrostatic capacity of the silicon. As a result, it is unable to do the test with a high frequency. In the conventional each system, the matching of the impedance of the wires is not done. This makes it impossible to test a fast semiconductor element or device. It means the conventional system cannot cope with the fast semiconductor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an equipment for testing an electric characteristic of a semiconductor device which is constructed to solve the foregoing problems and enable the test of a large area to be done, that is, test all the electrode pads of the wafer to be tested at a batch, thereby improving the manufacturing yield and reducing the manufacturing cost, by which method the inexpensive and highly reliable semiconductor device can be manufactured.
It is a further object of the present invention to provide a semiconductor testing equipment which is constructed to test a diversity of semiconductor elements or devices from a slow to a fast ones.
In order to achieve the objects, in a testing equipment for testing a semiconductor element by keeping an electrical connection between a plurality of electrode pads, which are formed on a semiconductor element to be tested, and probes which are formed on a first substrate made of silicon among a plurality of electric-connecting substrates located in the testing equipment, the probes are formed on a cantilever in the first substrate, and a wire is continuously connected from a tip of the probe to the electrode pad formed on an opposite side to a probe forming surface along a tip portion of the cantilever through an insulating layer.
In particular, in the first substrate having the probes formed thereon, a ground layer made of metal is formed within the first substrate, and a plurality of wires are formed on a surface of the ground layer through the insulating layer. A power line and a ground line of those wires are formed to be thicker than signal lines, and electrically conducted with the ground layer near the electrode pad. The signal lines are electrically conducted with the ground layer nearby the probe. Moreover, the thickness of the insulating layer may be preferably formed in the range of 3 &mgr;m to 30 &mgr;m.
Further, the first substrate is formed of low-resistive silicon, and a plurality of wires are formed on the surface of the first substrate through the insulating layer. The power line and the ground line of those wires are formed to be thicker than the signal lines, and are electrically conducted with the low-resistive silicon layer nearby the electrode pad. The signal li
Aoki Hideyuki
Ariga Akihiko
Endo Yoshishige
Hosogane Atsushi
Kanamaru Masatoshi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Vinh P.
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