Semiconductor device with a self-testing function and a...

Details Semiconductor device with a self-testing function and a... Semiconductor device with a self-testing function and a...

2001-05-07

2003-04-01

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S073100, C324S763010

Reexamination Certificate

active

06541994

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a self-testing function and a method for testing the semiconductor device, and more particularly, to a semiconductor device having a function to test a plurality of macro blocks and a method for testing the macro blocks.
2. Description of the Related Art
FIG. 7
is a block diagram for explaining a semiconductor device having a self-testing function and a method for testing the semiconductor device.
In the semiconductor device shown in
FIG. 7
, in a normal operation mode, input data Din is supplied to each of macro blocks
75
1
,
75
2
. and
75
m
, . . . Each of macro blocks
75
1
,
75
2
, . . . and
75
m
process the input data Din and output the processed data Dout.
In a test mode, test circuit
71
supplies test data (data used for testing) TTD to a circuit block
74
via a test bus
72
. The test data TTD is input to m (m represents an integer more than 1) macro blocks
75
1
,
75
2
, . . . and
75
m
in the circuit block
74
. Bus selectors
79
1
,
79
2
, . . . and
79
m
respectively included in the macro blocks
75
1
,
75
2
, . . . and
75
m
supply the test data TTD from the test circuit
71
to network circuits
76
1
,
76
2
, . . . and
76
m
. Each of the network circuits
76
1
,
76
2
, . . . and
76
m
process the test data TRD and output processed data TRD to the test circuit
71
through test buses
73
1
,
73
2
, . . . and
73
m
, respectively. The test circuit
71
compares the supplied processed data TRD with the expected value.
In the semiconductor device shown in
FIG. 7
, the test data TTD output from the test circuit
71
is supplied parallel to all of the macro blocks
75
1
,
75
2
, . . . and
75
m
, and processed parallel by the macro blocks
75
1
,
75
2
, . . . and
75
m
. Further, the respective processed data TRD of the macro blocks
75
1
,
75
2
, . . . and
75
m
are transmitted parallel to the test circuit
71
. Due to this parallelism, regardless of the number of the macro blocks
75
1
,
75
2
, . . . and
75
m
, time period required for the test is almost the same as time period for testing a single macro block.
FIG. 8
is a block diagram for explaining another example of a conventional semiconductor device having a self-testing function. In the semiconductor device shown in
FIG. 8
, a test circuit
81
supplies test data TTD to a circuit block
84
via a test bus
82
. A bus selector
89
i
(i represents an integer from 1 to m) selected by the test circuit
81
from among m bus selectors
89
1
,
89
2
, . . . and
89
m
respectively included in macro blocks
85
1
,
85
2
, . . . and
85
m
supplies the test data TTD to a network circuit
86
i
in the selected macro block
85
i
. The network circuit
86
i
processes the test data TTD and outputs processed data TRD. A bus selector
88
i
supplies the processed data TRD to the test circuit
81
via a test bus
83
. The test circuit
81
compares the received processed data TRD with the expected value.
The test circuit
81
repeats the above stated testing procedures for all the macro blocks, selecting one macro block at a time.
FIGS. 9A and 9B
are time charts showing the testing procedures of the semiconductor device shown in FIG.
8
. As known from
FIGS. 9A and 9B
, time period for testing the semiconductor device shown in
FIG. 8
is calculated by the equation below.
time period for testing the semiconductor device=(transmission time of the test data)×(number of macro blocks)+(time period for changing macro blocks)×(number of macro blocks−1)+delay time
The delay is caused by internal transmission of data in a macro block, most part of which is a time period required for data processing by a macro block.
The semiconductor device shown in
FIG. 7
requires the same number of test buses and circuits for comparing the processed data TRD with the expected data, as the number of macro blocks. Therefore, this semiconductor device requires a large occupation area.
The semiconductor device shown in
FIG. 8
cannot test a plurality of macro blocks parallel or at a time. Thus, if the number of macro blocks to be tested increases, more time is needed for testing those macro blocks.
An example of a semiconductor device which performs testing by individually transmitting test data to a plurality of macro blocks as shown in
FIG. 8
is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H2-10179. In testing, the semiconductor device disclosed in this publication selects a macro block to be tested under control by a test interface circuit equipped in each macro block, transmits test data to the selected macro block and tests this macro block individually. This disclosure is incorporated herein by reference.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device having a testing function and a method for testing a plurality of macro blocks in a short period of time.
It is another object of the present invention to provide a semiconductor device with a self-testing function which occupies a small area.
To achieve the above objects, a semiconductor device with a self-testing function according to the first aspect of the present invention comprises:
a first to n-th (n is an integer more than 1) macro blocks each of which receives input data, processes the input data, and outputs processed data;
a data path which supplies data to-be-processed to the n macro blocks, and transmits processed data processed by and output from the n macro blocks respectively, in a normal operation mode;
a test circuit which outputs test data for testing the n macro blocks and receives the test data processed by the n macro blocks, in a test mode; and
a test path which supplies the test data output from the test circuit to the first macro block, supplies data output from the h-th (h is an integer from 1 to (n−1)) macro block to the (h+1)th macro block and supplies data output from the n-th macro block to the test circuit.
The test path may comprise: a first test bus which transmits the test data output from the test circuit to the first macro block; connectors which transmit data output from the h-th macro block to the (h+1)th macro block; and a second test bus which transmits data output from the n-th macro block to the test circuit.
The test circuit may compare data received from the n-th macro block and an expected value, and detects that there is defect if received data substantially does not coincide with the expected value.
The test circuit may comprises: a supplier which supplies the test data; and a comparator which compares expected data with data received from the n-th macro block.
The test circuit may further comprise: a controller which designates j-th (j is an integer from 1 to n) macro block. In this case, it is desirable that the supplier supplies test data for testing the j-th macro block designated by the controller, the comparator compares expected data for the j-th macro block with data output from the j-th macro block, and the test path transmits the test data for testing the j-th macro block supplied from the supplier to the j-th macro block and supplies data output from the j-th macro block to the comparator.
For example, the controller performs control to test the j-th macro block individually, if any defect is found by the test circuit.
The test circuit may comprise a controller which designates j-th (j is an integer from 1 to n) macro block, a supplier which supplies test data for testing the j-th macro block designated by the controller, and a comparator which compares expected data for j-th macro block with data output from the j-th macro block. And the test path may further transmit the test data for testing the j-th macro block supplied from the supplier to the j-th macro block and supply data output from the j-th macro block to the comparator.
The semiconductor device may further comprise a second test path which supplies the test data to one of the macro

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