Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-07-01
2003-04-29
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S257000, C174S258000, C174S265000
Reexamination Certificate
active
06555762
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to printed circuit board and card manufacture and, more particularly, to a unique conductive composition for filling vias or through holes to make reliable vertical or Z-connects.
BACKGROUND OF THE INVENTION
With the continued trend toward reduced size of electronic components and the resulting high density requirements for electronic packaging, there has been an increased demand to design a process that will efficiently generate high quality, high density electronic packaging such as printed wiring board structures.
In the past decade the density per unit area of electronic devices, such as very large scale integrated circuits (VLSIs), has greatly increased. By some estimates this increase in density has been on the order of 10,000 times what it was in the earliest days of the technology. The space or area available outside of a VLSI in which to make the large number of necessary connections to and from it and to provide the necessary circuitry is becoming almost vanishingly small, measured by previous standards. Contrary to the density increase of VLSIs, the density of the passive circuits on printed wiring boards has increased (i.e., the parts have decreased in size) by only a relatively small factor: less than about 4 to 1. This presents the difficult problem of providing circuitry on the printed wiring board to the VLSIs which is small enough to fit the spaces available, while being sufficiently reliable and manufacturable to be economically useful.
Perhaps one of the most significant limitations for creating high density fine line circuitry on printed wiring boards is the generally known problem of anisotropic etching. It is known that etching metals, especially copper metal, is not an anisotropic process. That is, vertical etching is not feasible without some amount of unwanted horizontal etching. This creates a situation in which the features and circuitry so formed can be severely undercut, leading to different types of failures and reject material. The problem is exacerbated by having thick metal layers and thick photoresist layers. However, this is precisely the situation that occurs when plated through holes are part of conventional manufacturing process.
It is also well known that due to the nature of the plating process, the metal plating within a through hole or via is thinner than the plating on the external surfaces of the dielectric substrate; yet a minimum thickness in the through hole is required in order to provide an adequate and reliable electrical connection between circuitry on opposing surfaces or at various vertical levels within the printed wiring board structure. Therefore, the general practice is to plate excess material on the lateral faces in order to ensure sufficient plating of the through holes. The excessive thickness of the lateral surface plating causes greater amounts of undercutting during the later circuitization/etching process. To compensate for this effect, the circuitry lines are designed wider and farther apart than otherwise would be required or desired. In an attempt to resolve this problem, thinning down the lateral surface by uniform etching prior to circuitization has been attempted. If chemically performed, this process can also undesirably etch within the plated through hole. Mechanical etching of the lateral surface plating is possible, but requires an unacceptably long period of time.
Another difficulty in obtaining sufficient plating thickness within the through hole, as compared to plating the lateral surfaces, is the significant increase in expense associated with plating high aspect vias.
A land or pad around the through hole is required to provide a reliable electrical connection in the eventuality that there is a break in the plating on the rim of the through hole. The trade-off for applying a reliable land or pad is a thicker than necessary metallized region. Consequently, a thicker than usual photoresist layer must be applied to obtain a level surface for placement of the mask and to ensure the photoresist spanning over the hole (tenting) does not rupture and result in etchant entering the plated through hole. Thus, through holes cause an undesirable increase in thickness both of the surface plating and of the photoresist layer.
In addition to the problem of layer thickness discussed supra, the prior art process of plating through holes requires the land or pad on the lateral surface of the commoning layer to connect in a dog-bone configuration to the plated through holes. The land utilizes valuable space on the lateral surface that could otherwise be used for circuitry. Consequently, there has been a long standing desire to eliminate the need for such lands or pads.
The plated through hole itself also consumes valuable space for several reasons. Firstly, the diameter of the hole is typically dictated by the cost of plating high aspect vias and the cost of small diameter drilling bits. To avoid the expense of high aspect plated through holes, larger plated through holes are typically utilized, but they must be placed at a distance from the areas containing fine line circuitry. This design, known as “fan-out”, however, contributes to loss of circuitry space due to the need for greater routing space.
Another known problem associated with conventional plated through holes is the different expansion rate between copper plating and the dielectric or pre-preg layer. When subjected to heating and cooling cycles, the plating on the through hole is susceptible to cracking.
PRIOR ART REFERENCES
Prior art literature addresses the problems associated with plated through holes and describes processes and materials of making alternative designs. Relevant prior art patents are summarized hereinbelow.
Hayakawa et al. in U.S. Pat. No. 4,383,363, teach the benefit of using conductive materials for filling through holes. The patent is directed toward the process of filling through holes and describes only a limited selection of conductive fillers.
Lambert et al. in U.S. Pat. No. 4,820,340, disclose a method of fabricating a conductive polymer interconnect (CPI) which employs chains of electrically conductive particles within an elastomeric matrix. The process requires removing a thin layer of elastomeric material from the outer surfaces by use of plasma etching in order to provide a conductive surface. Gold- or silver-plated nickel particles are used, but no mention is made of using copper as the conductive material. Particles are approximately 100 micron and are imbedded in an elastomer of polysiloxane room temperature vulcanizing (RTV) rubber. Magnetic fields are used to align the particles and then a heat cure step is performed. Subsequently, the surface layer of the cured rubber is removed by plasma etching. As reported in Lambert, et al., U.S. Pat. No. 4,820,376, plasma etching removes the gold shell leaving the nickel core exposed to air. To prevent aerial oxidation of the nickel, the material is plated with electroless gold.
Kawakami et al. disclose, in U.S. Pat. No. 5,220,135, a conductive filling within the through hole of an insulative substrate. Conductive resins are described which include silver, copper, and carbon conductive materials. No mention is made of a core-shell particle having a fusible shell.
Higgins, III et al. in U.S. Pat. Nos. 4,967,314 and 5,117,069, describe a method and material for eliminating plating in through holes by filling the through holes with a silver epoxy conductive paste. Higgins, III et al. employ a process wherein the vias are slightly overfilled with the conductive epoxy in order to create bumps at each end of the via. Then several printed wiring boards and prepreg layers are stacked up and subsequently laminated. During the lamination process, the excess epoxy is squeezed from the ends and spreads out over the printed wiring board layer to create intimate contact between the circuitry and the conductive polymer within the through hole. Higgins, III et al. teach away from the use of a copper epoxy by indicating that the copper epoxy wo
Appelt Bernd K.
Gelorme Jeffrey D.
Kang Sung Kwon
Markovich Voya R.
Papathomas Kostas
Alcalá José H.
Fraley Lawrence R.
Salzman & Levy
Talbott David L.
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