Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-08-30
2003-05-13
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S754090, C324S765010
Reexamination Certificate
active
06563299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the design and testing of integrated circuit devices. Specifically, the present invention relates to the electrical characterization of integrated circuit device packages at high operating frequencies and, in particular, to apparatus and methods for measuring parasitic capacitance and inductance of one or more I/O leads of an integrated circuit device package using a network analyzer.
2. State of the Art
Designers of integrated circuit devices are facing increasingly difficult challenges as a result of the current trend toward integrated circuit devices exhibiting small overall package dimensions and having a large number of leads, yet being capable of operating at high frequencies. Such an integrated circuit device may include a complex array of closely spaced electrical leads adapted for establishing electrical communication with a semiconductor die, each lead having one end electrically connected to the semiconductor die and an opposing end adapted for electrical connection to an external device, such as a printed circuit board. Presently, a wide variety of integrated circuit package types and configurations are commercially available, including, for example, Ball Grid Array (BGA) packages, Thin Small Outline Packages (TSOPs), as well as other package types. It is a continuing goal of integrated circuit package designers to adapt these package configurations to fit within ever-decreasing volumes, to include a large number of electrical leads, and to operate at high frequencies in order to meet the demand for such devices.
An exemplary embodiment of a conventional BGA package is shown in
FIGS. 1 and 2
. The conventional BGA package
100
may be a memory device, such as a DRAM chip, a processor, or any other integrated circuit device known in the art. The conventional BGA package
100
includes a semiconductor die
110
secured to a die-attach pad
112
formed on an upper surface
106
of a substrate
105
, which may also be termed an interposer. The BGA package
100
also includes a plurality of electrical leads
130
adapted to provide electrical communication between the semiconductor die
110
and one or more external devices (not shown). The semiconductor die
110
and at least a portion of each electrical lead
130
may be encased by an encapsulant material
120
or, alternatively, the conventional BGA package
100
may have no encapsulant material, depending upon the particular package construction and intended use.
Each of the electrical leads
130
includes an external ball lead
132
configured for electrical connection to an external device. The ball lead
132
may be secured to a conductive pad
133
formed on a lower surface
107
of the substrate
105
. Each electrical lead
130
further comprises a conductive via
134
extending from the conductive pad
133
and through the substrate
105
to a conductive trace
136
. The conductive trace
136
is formed on the upper surface
106
of the substrate
105
and provides an electrical path from the conductive via
134
to a bond end
137
located proximate the semiconductor die
110
. A bond wire
138
attached to the bond end
137
of the conductive trace
136
and extending to the semiconductor die
110
, where the bond wire
138
is attached to a bond pad thereon, electrically connects the electrical lead
130
to the semiconductor die
110
. At least the bond wire
138
and conductive trace
136
of each electrical lead
130
may be encased by the encapsulant material
120
.
The conventional BGA package
100
may include a plurality of the ball leads
132
arranged, for example, in an array or arrays of mutually adjacent rows and columns. Referring to
FIG. 1
, the ball leads
132
may be arranged in two arrays
150
,
160
, each array
150
,
160
disposed between an edge of the semiconductor die
110
and a peripheral edge of the substrate
105
. Each array
150
,
160
comprises three columns
151
,
152
,
153
,
161
,
162
,
163
, respectively, of ball leads
132
. The arrangement of ball leads
132
is typically referred to as the “pin-out” or the “footprint” of the BGA package
100
. The pin-out of the BGA package
100
may, by way of example, comprise outer and inner columns
151
,
161
,
153
,
163
of ball leads
132
adapted to provide input and output of electrical signals to and from the semiconductor die
110
, such leads being referred to herein as “I/O leads.” The pin-out may further comprise center columns
152
,
162
of ball leads
132
adapted to provide a power signal to the semiconductor die
110
(a “V
CC
lead”), to provide a ground potential for the semiconductor die
110
(a “V
SS
lead”), or to provide a reference voltage to the semiconductor die
110
(a “V
REF
lead”). However, those of ordinary skill in the art will understand that the particular pin-out of an integrated circuit device may vary depending upon the application and that the pin-out may be of any suitable configuration.
An exemplary embodiment of a conventional TSOP is shown in
FIGS. 3 and 4
. The conventional TSOP
200
may be a memory device, such as a DRAM chip, a processor, or any other integrated circuit device known in the art. The conventional TSOP
200
includes a semiconductor die
210
secured to a die-attach pad
212
. The TSOP
200
further includes a plurality of electrical leads
230
adapted to provide electrical communication between the semiconductor die
210
and one or more external devices (not shown). The semiconductor die
210
and at least a portion of each electrical lead
230
are encased by an encapsulant material
220
.
Each of the electrical leads
230
includes an external portion
232
configured for electrical connection to an external device. Each electrical lead
230
also includes an internal portion
234
extending from the external portion
232
to a bond end
235
located proximate the semiconductor die
210
. A transversely extending bus bar or bars
239
may extend between two or more electrical leads
230
. A bond wire
238
electrically connects the bond end
235
of the internal portion
234
to a bond pad on the semiconductor die
210
to establish electrical communication therebetween. Bond wires
238
may also extend between the transverse bus bar or bars
239
and one or more bond pads on the semiconductor die
210
. At least the internal portion
234
and bond wire
238
of each electrical lead
230
are encased by the encapsulant material
220
.
The external portion
232
and internal portion
234
of each electrical lead
230
typically comprise a single piece of material commonly referred to as a lead finger. Further, the lead fingers (external and internal portions
232
,
234
), bus bar or bars
239
, and die-attach pad
212
typically comprise a structure usually referred to as a lead frame. Integrated circuit packages utilizing lead frame construction are well known in the art. It will be appreciated by those of ordinary skill in the art that the conventional TSOP
200
may include a lead frame of any configuration known in the art and, further, that the internal portion
234
may extend over and directly attach to the semiconductor die
210
, such a lead frame being commonly referred to as a Leads-Over-Chip (LOC) configuration.
The external portions
232
of the electrical leads
230
extend from one or more edges of the TSOP
200
and are arranged in a row therealong. For example, as shown in
FIG. 3
, the TSOP
200
may include a row
250
of electrical leads
230
extending from an edge of the TSOP
200
and another row
260
of electrical leads
230
extending from an opposing edge of the TSOP
200
. The arrangement of the external portions
232
of the electrical leads
230
comprises the pin-out or footprint of the TSOP
200
. An electrical lead
230
may be an I/O lead, a V
CC
lead, a V
SS
lead, or a V
REF
lead, as noted above, and the particular configuration of the pin-out will vary depending upon the application.
For both the conventional BGA package
1
Cuthbert David R.
Hedden Richard N.
Schoenfeld Aaron M.
Van Horn Mark T.
Karlsen Ernest
Micro)n Technology, Inc.
TraskBritt
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