Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-05-28
2003-04-15
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
Reexamination Certificate
active
06548883
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to wiring line formation and inter-line fill processes for a semiconductor substrate, and more particularly, to inter-line fill processes for reducing RC delay between adjacent wiring lines.
2. State of the Art
Integrated circuit substrates include many different p-type and n-type doped regions. These regions are connected in specific configurations to define desired devices and circuits. Conductive paths are defined on the substrate to connect the various doped regions to form the many devices and circuits. These paths typically are referred to as wires, interconnects, metal stacks, or conductors. The term “wiring line” is used herein to refer to all such conductive paths.
As device and circuit densities increase due to advances in technology, it is desirable to decrease wiring line pitches and spacings. A wiring line has a length, a thickness and a width. The non-line area between adjacent lines is referred to as the line spacing. The width and spacing is conventionally referred to as the line pitch. The spacing can be between lines on the same plane of the substrate or between lines on adjacent planes. Conventional line spacing of approximately 1.0 micron is known. There is a desire, however, to decrease line spacing as IC device densities increase.
One of the challenges of semiconductor processes is to maintain electrically-independent wiring lines. Electrical coupling between adjacent lines is undesirable. Reliable, uncoupled signals carried along adjacent lines are needed for normal circuit operation. One of the coupling characteristics between adjacent lines is the RC delay (“RC coupling”). Zero delay is ideal. Minimal RC delays are desired. As the spacing between two adjacent lines decreases, the RC coupling tends to increase. One of the physical characteristics defining RC delay (other than spacing) is the dielectric value of the fill material in the spacing between adjacent lines. Currently, dielectric values of approximately 3.0 are common for 1.0 micron line spacing. A dielectric of approximately 3.0 is achieved using tetra ethyl oxy silicate (“TEOS”) as the fill material between adjacent lines. Use of a high density plasma oxide fill at the 1 micron spacing has been found to achieve dielectric values between 2.4 and 2.7.
As the line spacings decrease (e.g., below 0.5 microns), new fill processes and materials are needed to avoid RC coupling and achieve minimal RC delays.
BRIEF SUMMARY OF THE INVENTION
According to the invention, a void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. The void is space absent solid and liquid material. In various embodiments the space is a vacuum or is filled with gaseous substance having desired dielectric properties.
According to one method of the invention, a hollow silicon dioxide sphere defines the void. The sphere is fabricated to a known inner diameter, wall thickness and outer diameter. Preferably, the wiring line height is a multiple of the line spacing, or the spacing is a multiple of the wiring line height. Spheres of a unit dimension then fill the spacing to achieve one or more rows (or columns) of spheres.
According to one aspect of the method, the spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication.
The spheres are held in place during the semiconductor fabrication processes by a binder. According to another aspect of the method, the spheres and binder withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the binder is baked away leaving the sphere intact and in place.
According to another method of the invention, the adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). In a specific embodiment, the cross section appears as a “T” or as an “I.” Dielectric fill is deposited in the spacing between lines by a chemical vapor deposition (“CVD”) or other deposition process. As the dielectric material accumulates on the wiring line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void. Using controlled processes, the void is reliably defined to a known size and shape.
According to preferred embodiments, a spacing between adjacent wiring lines of a semiconductor substrate includes a first material which defines a void. The void has no solid material or liquid material, but may include a gas. Also, the void is characterized by a dielectric constant which is lesser than the dielectric constant of the first material. In one embodiment, a plurality of discrete hollow objects fill the spacing. Each one of the plurality of objects is a hollow, rigid, silica sphere which defines a void. Each sphere is of substantially the same dimensions. The spacing between adjacent lines is approximately a first multiple of sphere outer diameter. The height of the adjacent wiring lines is approximately a second multiple of sphere outer diameter. Preferably, either one, but not both, of the first multiple and the second multiple are greater than one.
According to a preferred embodiment of one method, a void is controllably-defined in spacing between adjacent wiring lines of a semiconductor substrate. At one step, a plurality of discrete hollow silica spheres are applied to the spacing. At another step, excess spheres are removed from areas other than the spacing. At another step, material is deposited over the wiring lines and spheres. For one method, the spheres are applied as part of a film, including a binder. The binder holds the objects in place within the spacing. For one method, the excess spheres are removed by performing a chemical-mechanical polishing (“CMP”) process. Preferably, the deposition step occurs at a temperature sufficient to break down the binder while leaving the spheres in place and intact.
According to another preferred embodiment, a void is controllably-defining in spacing between adjacent wiring lines of a semiconductor substrate using an alternative method. At one step, a T-top configuration is etched at each of the adjacent wiring lines. At another step, dielectric material is deposited onto the substrate and adjacent wiring lines. The deposited material accumulates about the T-tops to seal off a void in the spacing. The void forms with dimensions determined by the spacing, wiring line height, and undercut of the T-tops. For various alternatives, the wiring line cross-sections after T-topping resemble an “I” or a “T” configuration.
REFERENCES:
patent: 3978269 (1976-08-01), Martin
patent: 4039480 (1977-08-01), Watson et al.
patent: 4141055 (1979-02-01), Berry et al.
patent: 4450184 (1984-04-01), Longo et al.
patent: 4781968 (1988-11-01), Kellerman
patent: 4917857 (1990-04-01), Jaeckel et al.
patent: 5126192 (1992-06-01), Chellis et al.
patent: 5192715 (1993-03-01), Sliwa, Jr. et al.
patent: 5278103 (1994-01-01), Mallon et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5372969 (1994-12-01), Moslehi
patent: 5407860 (1995-04-01), Stolz et al.
patent: 5413962 (1995-05-01), Lur et al.
patent: 5468685 (1995-11-01), Orisaks et al.
patent: 5506173 (1996-04-01), Nishimoto
patent: 5510645 (1996-04-01), Fitch et al.
patent: 5523615 (1996-06-01), Cho et al.
patent: 5559055 (1996-09-01), Chang et al.
patent: 5599745 (1997-02-01), Reinberg
patent: 5708303 (1998-01-01), Jeng
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5776823 (1998-07-01), Givens
patent: 5814888 (1998-09-01), Nishioka et al.
patent: 5835987 (1998-11-01), Givens
patent: 5847439 (1998-12-01), Reinberg
patent: 6004832 (1999-12-01), Haller et al.
patent: 6048802 (2000-04-01), Avanzino et al.
patent: 363293950 (1988-11-01), None
patent: 404079333 (1992-03-01), None
Ohkura et al., “A Novel Global Planarization Process Using Gap Filling With Self-Aligned Silica Spacer,” VMIC Conference, Jun. 27-29, 1995 (1995 ISMIC—104/95/0233).
Pawloski, “The Science and Engineering of Thermal Spray Coatings,” p. 20, John Wiley and Sons.
Bulletin #
Micro)n Technology, Inc.
TraskBritt
Wilson Allan R.
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