Multiplied clock generating circuit

Details Multiplied clock generating circuit Multiplied clock generating circuit

2002-03-15

2003-05-06

Callahan, Timothy P (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

06559697

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2001-75934 filed on Mar. 16th, 2001; the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to digital circuits, and more particularly relates to a multiplied clock generating circuit for generating and outputting a times-M clock signal that has a higher frequency than an arbitrary input clock by a factor M.
2. Description of the Related Art
FIG. 1
is a schematic diagram showing an example of a multiplied clock generating circuit for generating a feedback clock signal fd by dividing an output clock signal fo by M and controlling the frequency and the phase of the feedback clock signal fd to match those of an input clock signal fr. In the figure, the multiplied clock generating circuit is composed of a frequency divider circuit
101
, a phase comparator circuit
102
, a frequency comparator circuit
103
, a clock phase synchronization circuit
104
, an oscillator control circuit
105
and an oscillator circuit
106
.
The frequency divider circuit
101
serves to generate the feedback clock signal fd by dividing by M the output clock signal fo while the phase comparator circuit
102
serves to detect the phase difference between the input clock signal fr and the feedback clock signal fd and output the result of detection to the frequency comparator circuit
103
and the clock phase synchronization circuit
104
. The frequency comparator circuit
103
and the clock phase synchronization circuit
104
serve to calculate how much the output clock signal fo should be modified for adjusting the frequency and the phase of the feedback clock signal fd to the input clock signal fr on the basis of information given by the phase comparator circuit
102
, and outputting the results to the oscillator control circuit
105
. The oscillator control circuit
105
takes control of the oscillator circuit
106
to modify the output clock signal fo on the basis of the information as given from the frequency comparator circuit
103
and the clock phase synchronization circuit
104
.
FIG. 2
is a schematic diagram showing an example of the configuration of the oscillator circuit
106
. In the figure, the oscillator circuit
106
is composed of a fixed-delay-time delay circuit
111
, a variable-delay-time delay circuit
112
and an oscillation control circuit
113
. The variable-delay-time delay circuit
112
is composed of four variable-delay-time delay cells (dcell)
114
. The delay time of each variable-delay-time delay cell
114
is (d+&Dgr;d) when the signal dlysw*(*=0 to 3) is set to a low level and is d when the signal dlysw*(*=0 to 3) is set to a high level. When a signal osc_act is low, the output clock signal fo is fixed to a low level by the oscillation control circuit
113
so that the oscillation of the oscillator circuit is halted. Accordingly, the oscillator control circuit
105
receives the information from the frequency comparator circuit
103
and the clock phase synchronization circuit
104
and takes control of the variable-delay-time delay cell
114
in order to modify the delay time thereof.
For example, if the input signals to the variable-delay-time delay cells
114
are fixed dlysw
3
=dlysw
2
=low and dlysw
1
=dlysw
0
=high so that the feedback clock signal fd has a frequency &tgr;
1
lower than that of the input clock signal fr while the input signals to the variable-delay-time delay cells
114
are fixed dlysw
3
=low and dlysw
1
=dlysw
0
=dlysw
2
=high so that the feedback clock signal fd has a frequency &tgr;
2
higher than that of the input clock signal fr, then the input signals to the variable-delay-time delay cells
114
are fixed such that dlysw
3
=low and dlysw
1
=dlysw
0
=high while the signal dlysw
2
is controlled by maintaining or inverting it for each cycle of the feedback clock signal fd in order to the clock period of the feedback clock signal fd is either &tgr;
1
or &tgr;
2
as illustrated in the timing chart of FIG.
3
.
FIG. 3
is a timing chart in which the phase of the feedback clock signal fd is adjusted in order that the rising edge of the feedback clock signal fd coincides with the rising edge of the input clock signal fr. Since the rising edge edge
0
of the feedback clock signal fd is advanced ahead of the rising edge of the input clock signal fr, the clock period of the feedback clock signal fd starting from the rising edge edge
0
is set to &tgr;
1
which is longer than the clock period of the input clock signal fr. On the other hand, since the rising edge edge
1
lags behind the rising edge of the input clock signal fr, the clock period of the feedback clock signal fd starting from the rising edge edge
1
is then set to &tgr;
2
, which is shorter than the clock period of the input clock signal fr and maintained until the rising edge edge
4
appears from which the rising edge of the feedback clock signal fd is advanced again ahead of the rising edge of the input clock signal fr. Thereafter, the clock period of the feedback clock signal fd starting from the rising edge edge
4
is set to &tgr;
1
which is longer than the clock period of the input clock signal fr while the clock period of the feedback clock signal fd starting from the rising edge edge
5
is set to &tgr;
2
in the same manner.
Also, as illustrated in
FIG. 3
, if the multiplication factor of the input clock signal fr is M, the period &tgr;
1
and the period &tgr;
2
are calculated as
&tgr;
1
=[(
d+&Dgr;d
)×2
+d×
2]×2×
M
&tgr;
2
=[(
d+&Dgr;d
)×1
+d×
3]×2×
M.
and therefore the difference between the period &tgr;
1
and the period &tgr;
2
is calculated as
&tgr;
1
−&tgr;
2
=
M×&Dgr;d×
2.
The difference between the period &tgr;
1
and the period &tgr;
2
ensues jittering of the feedback clock signal fd and, understood from the above described equations, the amount of jittering becomes large as the multiplication factor M becomes large so that it can be the case that the specification of the system can not be satisfied.
FIG. 4
is a timing chart showing the relationship among the feedback clock signal fd, the output clock signal fo, the signal dlysw
2
and the input clock signal fr as described above, in which FIG.
4
(
a
) is a graphic diagram showing the feedback clock signal fd with the clock period of &tgr;
1
; FIG.
4
(
b
) is a graphic diagram showing the feedback clock signal fd with the clock period of &tgr;
2
; and FIG.
4
(
c
) is a graphic diagram showing the input clock signal fr. As illustrated in
FIG. 4
, while the clock period of the feedback clock signal fd switches between the period &tgr;
1
and the period &tgr;
2
, the output clock signal fo has the jitter of (&Dgr;d×2) while the feedback clock signal fd has the jitter of (M×&Dgr;d×2).
FIG. 5
is a graphic diagram showing the relationship between the jitter of the feedback clock signal fd and the jitter of the variable delay &Dgr;d with reference to the multiplication factor M in the case where the output frequency of the output clock signal fo is fixed to a desired value. In the figure, when a higher frequency output clock signals is desired, it is understood that the variable delay &Dgr;d has to be set to a smaller value in order to suppress the jitter of the feedback clock signal fd.
In contrast with this, with the recent advent of high speed semiconductor devices and therefore the increase in the clock frequency as required in the system for keeping pase therewith, a higher multiplication factor is increasingly required of the multiplied clock generating circuit. Because of this, it is difficult to generate an output clock with a higher multiplication factor simply by controlling the variable delay &Dgr;d as illustrated in FIG.

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