Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-05-17
2003-07-01
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S692000, C257S697000, C257S773000
Reexamination Certificate
active
06586830
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P2000-147836 filed May 19, 2000, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, an interposer thereof, and a method of manufacturing the same, and in particular, the present a invention relates to a semiconductor device having a CSP (Chip Size Package or Chip Scale Package) structure, an interposer thereof, and a method of manufacturing the same.
In order to cope with a demand for a compact design of recent electronic products, necessity of a high density packaging for electronic parts, in particular, for semiconductor devices is increasing. Therefore, a CSP (Chip Size Package) is adopted as one of such high density packages instead of a conventional plastic package.
An internal structure of the CSP can be divided roughly into two types depending on a method of interconnection between electrodes of an IC (Integrated Circuit) chip (which may be referred to also as a chip or a semiconductor chip hereinafter) and an interposer (wiring board). One of two types of the CSP is a wire bonding type CSP as indicated in
FIG. 16
, wherein after connecting an interposer
21
A and electrodes of an IC chip
10
to each other with a copper wire
17
, they are packaged with a resin
18
to form a semiconductor package
20
, which is then connected to a mounting substrate via a solder bump
11
.
The other type is a flip-chip type CSP as indicated in
FIG. 17
, wherein an IC chip
10
and an electrode
23
of an interposer
21
are connected to each other via a solder bump
22
, and an under-fill material is filled in a gap between the IC chip
10
and the interposer
21
to form a package
25
, which is then connected to a mounting substrate via a solder bump
11
.
Although the wire bonding type CSP will provide a cheaper package, there is, however, such a disadvantage that the package size becomes larger than its chip size because of a necessity of an additional space for accommodating its wiring. On the other hand, the flip-chip type CSP has such an advantage that the package size can be reduced. Therefore, in order to cope with an increasing demand for compact design of recent electronic products, the flip-chip type packaging is increasing.
Further, as for a structure of external electrodes of the CSP, there are two types. One of them is shown in
FIG. 18
, which has a ball grid array type structure provided as a package's lower surface electrode which functions as external electrodes of the CSP. The other one shown in
FIG. 19
has a land grid array type structure which is comprised only of electrodes
24
of the interposer
21
A without using the solder ball.
Interconnection between the semiconductor package and a mounting substrate (which may be referred to also as a substrate hereinafter) in both cases of the above is carried out by a solder bonding technique in which the solder on the substrate is fused in an oven, then solidified.
FIG. 20
shows a state of a module after packaging.
As for a reliability of a semiconductor package manufactured as described above, in particular, in its heat cycle test, while in consideration that a cause of most of failures is due to a difference of linear expansion coefficient between the semiconductor chip and the mounting substrate (a linear expansion coefficient of the semiconductor chip: 3 to 4 ppm/a linear expansion coefficient of the mounting substrate: 15 to 20 ppm), however, because the semiconductor package has a sandwich structure with the interposer
21
interposed between the semiconductor chip
10
and the mounting substrate
13
thereby spacing apart both of them at a distance, and thereby attempting to relieve or absorb a stress or strain due to thermal expansion and contraction of the semiconductor chip
10
and the mounting substrate
13
.
However, because of an increasing number of terminal pins needed for a large scale integration of a semiconductor integrated circuit, miniaturization in the size of solder balls for interconnection between the semiconductor package (CSP) and the mounting substrate is advancing, and now, a size of solder balls smaller than 300 &mgr;m in comparison with a conventional size of 800 &mgr;m is emerging. In addition, a size of the package is also being large-scaled. Therefore, it is becoming very difficult to guarantee a package reliability for the package module which has the above-mentioned CSP mounted on the mounting substrate in the conventional manner described above.
More specifically, in an accelerated heat cycle testing for determining the package reliability, it is becoming more difficult for the conventional interposer
21
to be able to relax the stress due to the thermal expansion and contraction. Namely, because of a relatively large difference in linear expansion coefficients between the IC chip
10
and the mounting substrate
13
, the IC chip
10
and the interposer
21
cannot follow a large contraction of the mounting substrate
13
at the time of its contraction after expansion, thereby allowing the mounting substrate
13
having a large degree of expansion and contraction to warp at its non-contacting portion at the time of contraction, and thereby damaging the solder for interconnection. Therefore, as a result, a failure mode such as ruptures of inner bumps A as shown in FIG.
21
and secondary connection solder bumps B as shown in
FIG. 21
is likely to occur.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above-mentioned problems associated with the conventional art, and to provide a semiconductor device and its interposer having a semiconductor package structure capable of realizing an improved package reliability, and a method of manufacturing the same.
That is to say, the present invention is directed to a provision of a semiconductor device having a structure in which an external terminal or a conductive part (It may be a thin electrode) connected thereto is interposed, with a predetermined length (for example, 100 to 300 &mgr;m) thereof being exposed, in a gap between a semiconductor chip and a mounting substrate for mounting the semiconductor chip thereon.
In the semiconductor device according to the invention, the external terminal or the conductive part connected thereto which is interposed, with the predetermined length thereof being exposed, in the gap between the semiconductor chip and the mounting substrate is allowed to deform in response to a differential expansion coefficient between the semiconductor chip and the mounting substrate due to a thermal stress at the time of packaging of the semiconductor chip and/or in use after packaging, and therefore, this deformation allows to absorb a mechanical stress at the time of cooling caused by a difference in contraction between the semiconductor chip and the mounting substrate having a different expansion coefficient to each other. As a result, a highly reliable interconnection at each portion between the semiconductor chip and the mounting substrate is ensured to be maintained, thereby providing a semiconductor device featuring a very high package reliability.
Further, the present invention is directed to a provision of a method of manufacturing the semiconductor device, the method comprises the steps of: interposing an external terminal or a conductive part (It may be a thin electrode) to be connected to the external terminal, with a predetermined length thereof being exposed, in a gap between a semiconductor chip and a mounting substrate for mounting the same; and coating the other portion of the external terminal excepting the exposed portion having the predetermined length with a conductive material.
According to the method of manufacturing the semiconductor device of the invention, wherein a same semiconductor device as the semiconductor device of the invention described above can be fabricated, there can provided a method of manufacturing the semiconductor device having t
Depke Robert J.
Holland & Knight LLC
Wilson Allan R.
LandOfFree
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