Single chip CMOS transmitter/receiver

Details Single chip CMOS transmitter/receiver Single chip CMOS transmitter/receiver

2001-07-05

2003-01-21

Pham, Chi (Department: 2631)

Pulse or digital communications

Receivers

Angle modulation

C375S339000, C327S213000

Reexamination Certificate

active

06510185

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a communication system, and in particular, to a CMOS radio frequency (RF) communication system.
2. Background of the Related Art
Presently, a radio frequency (RF) communications system has a variety of applications including PCS communication and IMT systems. As such, a CMOS chip integration of the system has been pursued to reduce the cost, size and power consumption.
Generally, the RF communication system is composed of RF front-end block and base-band digital signal processing (DSP) block. Currently, the base-band DSP block can be implemented with low cost and low power CMOS technology. However, the RF front-end cannot be implemented by CMOS technology because of limitations in speed and noise characteristics, which are below the speed and noise specification of popular RF communication systems.
For example, the PCS hand-phone systems operate at a frequency over 2.0 GHz, but current CMOS technology reliably operates only up to approximately 1.0 GHz in terms of speed and noise. Hence, the RF front-end block is implemented using bipolar or bi-CMOS technology that has better speed and noise characteristics than CMOS technology but is more expensive and consumes more power.
Currently, two different types of RF architecture called “direct conversion” and “double conversion” are used for CMOS RF communication systems. Both architectures have advantages and disadvantages in terms of CMOS implementations.
FIG. 1
is a diagram showing a related art direct conversion RF system
100
. The related art direct conversion CMOS RF communication system
100
includes an antenna
105
, a RF filter
110
, a low noise amplifier (LNA)
120
, a first mixer
140
, a second mixer
145
, a phase-locked loop (PLL)
130
, a first low pass filter (LPF)
150
, a second LPF
155
, a first analog/digital (A/D) converter
160
, a second A/D converter
165
, a third mixer
160
and a power amplifier
170
.
The antenna
105
receives RF signals and selected RF signals are then filtered at the RF filter
110
. The filtered RF signals are amplified with a gain at the LNA
120
and the RF signals passing through the LNA
120
are directly demodulated into base band signals by quadrature multiplication at the first and second mixers
140
and
145
. The PLL
130
preferably generates two types of clock signals, I signals and Q signals using a voltage controlled oscillator (VCO). The I clock signals and the Q clock signals are the same excepting a phase difference. I signals preferably have a phase difference of 90 degrees from Q signals. That is, Q signals are phase shifted with respect to quadrature phase shift I signals. The two sets of signals I and Q are preferably used to increase the ability of the RF system to identify or maintain received information regardless of noise and interference. Sending two types of signals having different phases reduces the probability of information loss or change. A demodulation frequency f
0
in
FIG. 1
is equal to a modulation frequency f
0
.
As shown in
FIG. 1B
, the demodulated based band signals have a frequency reduced by the frequency f
0
from an original frequency to pass through the first and second LPF
150
and
155
and eventually become respective signals required for A/D conversion at the first and second A/D converters
160
and
165
. The digital signals are then transferred to a base-band discrete-time signal processing (DSP) block (not shown). Channel selection is performed by changing frequency f
0
in at the phase-locked loop (PLL)
130
.
As described above, the related art direct conversion RF system
100
has advantages for CMOS RF integration because of its simplicity. In the related at direct conversion RF system only a single PLL is required. Further, in the related art direct conversion RF system high-quality filters are not required. However, related art the direct conversion architecture has disadvantages that make single chip integration difficult or impossible. As shown in
FIG. 2A
, clock signals cos &ohgr;
LO
t from a local oscillator (LO) such as the VCO may leak to either the mixer input or to the antenna where radiations may occur because the local oscillator (LO) is at the same frequency as the RF carriers. The unintentionally transmitted clock signals &Dgr;(t) cos &ohgr;
LO
t signals can reflect off nearby objects and be “re-received” by the mixer again. The low pass filter outputs a signal M(t) +&Dgr;(t) because of leakages of clock signals. As shown in
FIG. 2B
, self-mixing with the local oscillator results in problems such as time variations or “wandering” DC-offsets at the output of the mixer.
FIG. 2B
illustrates time variations and a DC-offset. A denotes a signal before the mixer and B denotes a signal after the mixer. The time-varying DC-offset together with inherent circuit offsets significantly reduce the dynamic range of the receiver portion. In addition, a direct conversion RF system requires a high-frequency, low-phase-noise PLL for channel selection, which is difficult to achieve with an integrated CMOS voltage controlled oscillator (VCO).
FIG. 3
shows a block diagram of a related art RF communication system
300
according to an double conversion architecture that considers all of the potential channels and frequency transistors. As shown in
FIG. 3
, the RF communication system
300
includes antenna
305
, a RF filter
310
, a LNA
320
, a first mixer
340
, a second mixer
345
, a first LPF
350
, a second LPF
355
, second stage mixers
370
-
373
, a first adder
374
, a second adder
375
. The RF communication system
300
further includes a third LPF
380
, a fourth LPF
385
, a first A/D converter
390
, a second A/D converter
395
, first and second PLLs
330
and
335
, a third mixer
360
and a power amplifier
370
.
The mixers
340
,
345
and
370
-
373
are all for demodulation while the third mixer
360
is for modulation. The first and second mixers
340
and
345
are for a selected RF frequency and the mixers
370
-
373
are for an intermediate frequency (IF). The first PLL
330
generates clock signals at a high frequency or the RF frequency, the second PLL
335
generates clock signals having a low frequency or the intermediate frequency (IF).
Transmission data are multiplied with the clock signals having the RF frequency from the PLL
330
to have a frequency reduced by the RF frequency from an original transmission data frequency. The output signals of the third mixer
360
are amplified with a gain at the power amplifier
370
and then radiated through the antenna
305
for transmission.
For reception data the antenna
305
receives RF signals and the RF filter
310
filters the RF signals. The filtered RF signals are amplified by the LNA
320
and are converted into IF signals by the quadrature mixers
340
,
345
with a single frequency local oscillator, generally a VCO. The PLL
330
generates clock signals for I signals of the RF signals and generates clock signals for Q signals of the RF signals. The mixer
340
multiplies the RF signals with the clock signals for the I signals having the RF frequency and the mixer
345
multiplies the RF signals with the Q signals having the RF frequency. The LPFs
350
,
355
are used at an IF stage (i.e., first stage) to remove any frequency components not converted upon conversion to the IF signals, which allows all channels to pass to the second stage mixers
370
-
373
. All of the channels at the IF stage are then frequency-translated directly to base-band frequency signals by the tunable PLL
335
for channel selection.
Demodulated base band signals C pass low pass filters (LPF)
380
and
385
and are converted into digital data by A/D converters
390
and
395
. The digital data is then transferred into a base-band discrete-time signal processing (DSP) block (not shown).
As described above, the related art double conversion RF system
300
has various advantages. The related art double conversion RF system
300
performs the channel tuning using the lower-fre

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