Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-04-30
2003-03-18
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S765010
Reexamination Certificate
active
06535015
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally devices and methods for testing the performance of silicon structures, and more specifically to an integrated circuit for testing the floating body effect of silicon on insulator integrated circuit structures.
BACKGROUND OF THE INVENTION
Silicon on Insulator (SOI) technology refers to integrated circuit technology for forming field effect transistors (FETs), and other SOI structures, in a thin layer of silicon positioned above a layer of insulating material.
Utilizing SOI technology, an SOI wafer is formed from a bulk silicon wafer by using conventional oxygen implantation techniques or wafer bonding techniques to create a buried silicon dioxide insulating layer at a predetermined depth below the surface of the wafer. Between the insulating layer and the surface is a thin layer of silicon wherein SOI structures are fabricated and isolated from other SOI devices formed therein utilizing SOI fabrication processes.
The advantages of SOI circuits over conventional bulk semiconductor circuits include: i) reduced size because electrical isolation of each SOI FET utilizes less surface area than required utilizing bulk technology; ii) reduced power consumption because junction capacitance between the source/drain and off state leakage from the drain to the source are both less for an SOI FET than a bulk FET; and iii) increased operating speed because the reduced junction capacitance increases the speed at which a device can operate.
However, a problem associated with SOI FETs is known as the floating body effect. The floating body effect occurs because the buried oxide layer isolates the channel, or body, of the FET from the fixed potential silicon substrate. Therefore the body takes on charge based on historical operation of the transistor. The floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate. This problem is particularly apparent for pass gate devices such as those used in dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the “Off” position to prevent charge leakage from the storage capacitor.
Accordingly, it is desirable for the FET to have a structure which minimizes the floating body effect, or at the least, optimizes a trade off of performance characteristics, including the floating body effect, based on the circuits desired operating characteristics. Because the SOI FET structure is determined by the SOI fabrication process parameters, adjusting the process parameters will alter the FET structure and performance. Typically, performance parameters are optimized using an empirical and iterative process wherein i) test structures are made utilizing trial fabrication parameters, ii) performance of the test device are measured, and iii) fabrication parameters are adjusted for fabrication of the next test device.
Typically the testing is performed by coupling the test SOI structures to I/O leads. Test signals are generated on a remote signal generation device and coupled to the I/O leads for driving the test SOI structures. The response signals are coupled to remote measurement circuits (again via the I/O leads) for measuring the response of the test structures to the test signals.
A problem associated with such testing systems is that the measurement accuracy is distorted by 1) signal degradation of the test signals caused by noise on wires or traces. which couple the test signals to the test SOI structures; 2) signal degradation of the response signals caused by noise on the wires or traces which coupled the response signals from the test SOI structures to the remote measurement circuits; and 3) signal degradation of both the test signals and response signals caused by I/O circuits which are required for appropriately isolating, ESD protecting, and coupling SOI structures to “off chip” circuits.
Accordingly, there is a strong need in the art for a device and method for testing performance of trial silicon on insulator structures that does not suffer the disadvantages of known systems.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a single wafer test circuit for testing performance of a silicon on insulator circuit structure. The circuit is fabricated on the wafer and includes a circuit structure or, device under test (DUT), on which performance testing is to be performed. In addition an input circuit is fabricated on the wafer, and coupled to the DUT, for generating a drive signal for operating the DUT. An output circuit structure is also fabricated on the wafer, and coupled to the DUT, for generating an output signal representative of the response of the DUT to the drive signal. Metal layer circuits formed on the wafer above the DUT couple the DUT to each of the input circuit structure and the output circuit structure.
The input circuit may include a clock circuit generating. a plurality of clock signals, each at a different clock frequency, and a select circuit for selecting a combination of one or more of the plurality of clock signals to generate the drive signal at a desired frequency and duty cycle. An oscillator may generate a high frequency clock signal and a plurality of counters may each generate one of the plurality of clock signals at a fractional frequency of the high frequency clock signal.
Further, the input circuit may include a load circuit with a plurality of capacitive loads, each of a different capacitance, and a load select circuit for selecting one of the plurality of capacitive loads for coupling to the selected one of the clock signals for generating the drive signal.
A wafer input circuit may couple each of power and ground to the wafer and may also provide appropriate isolation for coupling each of the clock select signal to the clock select circuit and a load select signal to the load select circuit.
The output circuit may include an integrator generating a voltage signal in accordance with a current characteristic of the response signal. A wafer output circuit may provide appropriate isolation and amplification for coupling the output signal to an off chip measurement and evaluation device.
The DUT may be a silicon on insulator field effect transistor and the output signal may represent at least one of rise and fall time of the FET in response to the drive signal coupled to a gate of the FET. Alternatively, the output signal may represent current through the FET in response to a voltage of the drive circuit applied to a gate of the FET.
A second aspect of the present invention is to provide a method of testing performance of a DUT. The method comprises driving the DUT with a drive signal generated on the silicon on insulator wafer and processing a response signal from the DUT on the silicon on insulator wafer to generate an output signal representing the response signal.
The step of driving the DUT with a drive signal generated on the silicon on insulator wafer includes generating a plurality of clock signals, each at a different clock frequency, and selecting a combination of one or more of the plurality of clock signals to generate the drive signal at a desired frequency and duty cycle. More specifically, the step may include generating a single clock signal of a first frequency and generating the plurality of clock signals, each at a different fractional frequency of the first frequency. A remote clock select signal may be coupled to the wafer for selecting one of the plurality of clock signals.
The step of driving the DUT may also include coupling the selected one of the plurality of clock signals to a selected one of a plurality of capacitive loads. A remote load select signal may be coupled to the wafer for selecting of the plurality of capacitive loads.
The step of processing a response signal from the silicon on insulator circuit structure on the silicon on insulator wafer to generate an output signal representing the response signal includes integrati
En William G.
Ju Dong-Hyuk
Klein Richard K.
Krishnan Srinath
Lee Siu Lun
Cuneo Kamand
Nguyen Jimmy
Renner Otto Boisselle & Sklar
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